Change in coreboot[master]: soc/amd/stoneyridge: Replace public magic numbers

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29198

Change subject: soc/amd/stoneyridge: Replace public magic numbers
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soc/amd/stoneyridge: Replace public magic numbers

Some "magic" numbers became public available registers/bits after the code
was originally written. Find all magic numbers, and if available in a public
BKDG than replace them with literals.

BUG=b:117648026
TEST=Build and boot grunt.

Change-Id: I96ac59fd92c4a5e27c3836f77bf6633e9b0c4990
Signed-off-by: Richard Spiegel 
---
M src/soc/amd/stoneyridge/include/soc/northbridge.h
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/southbridge.c
4 files changed, 13 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29198/1

diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 7f7ac5d..94f9d90 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -62,9 +62,15 @@
 # define MMIO_RE		(1 << 0)
 #define D18F1_MMIO_LIMIT0_LO	0x84
 # define MMIO_NP		(1 << 7)
+#define D18F1_IO_BASE0_LO	0xc0
+#define D18F1_IO_BASE1_LO	0xc8
+#define D18F1_IO_BASE2_LO	0xd0
+#define D18F1_IO_BASE3_LO	0xd8
+#define D18F1_MMIO_BASE7_LO	0xb8
 #define D18F1_MMIO_BASELIM0_HI	0x180
 #define D18F1_MMIO_BASE8_LO	0x1a0
 #define D18F1_MMIO_LIMIT8_LO	0x1a4
+#define D18F1_MMIO_BASE11_LO	0x1b8
 #define D18F1_MMIO_BASELIM8_HI	0x1c0
 #define NB_MMIO_BASE_LO(reg)	((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \
    				? D18F1_MMIO_BASE0_LO \
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 681f149..7355f72 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -304,6 +304,7 @@
 #define LPC_WIDEIO2_GENERIC_PORT	0x90

#define SPIROM_BASE_ADDRESS_REGISTER	0xa0
+#define   SPI_BASE_RESERVED		(BIT(5) | BIT(6))
 #define   ROUTE_TPM_2_SPI		BIT(3)
 #define   SPI_ABORT_ENABLE		BIT(2)
 #define   SPI_ROM_ENABLE		BIT(1)
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index c6e84b3..8c7dc31 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -401,7 +401,7 @@
    	base = pci_read_config32(SOC_ADDR_DEV, reg);
    	limit = pci_read_config32(SOC_ADDR_DEV, reg + 4);
    	/* Is this register allocated? */
-		if ((base & 3) != 0) {
+		if ((base & MMIO_WE) || (base & MMIO_RE)) {
    		unsigned int reg_link, index;
    		struct resource *res;

@@ -419,10 +419,10 @@
 {
    /* Be sure all domain resources are reserved */
    /* MMIO */
-	reserve_domain_res(0x80, 0xb8);
-	reserve_domain_res(0x1a0, 0x1b8);
+	reserve_domain_res(D18F1_MMIO_BASE0_LO, D18F1_MMIO_BASE7_LO);
+	reserve_domain_res(D18F1_MMIO_BASE8_LO, D18F1_MMIO_BASE11_LO);
    /* IO */
-	reserve_domain_res(0xc0, 0xd8);
+	reserve_domain_res(D18F1_IO_BASE0_LO, D18F1_IO_BASE3_LO);

pci_domain_read_resources(dev);
 }
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 37ebdc1..b188b76 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -414,8 +414,8 @@

/* Make sure the base address is predictable */
    base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
-	enables = base & 0xf;
-	base &= ~0x3f;
+	enables = base & SPI_PRESERVE_BITS;
+	base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED);

if (!base) {
    	base = SPI_BASE_ADDRESS;