Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84328?usp=email )
Change subject: soc/intel/xeon_sp/gnr: Enable IRQ routing ......................................................................
soc/intel/xeon_sp/gnr: Enable IRQ routing
Enable IRQ routing per PCH IRQ usage convention and report domain _PRT.
Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba Signed-off-by: Lu, Pen-ChunX pen-chunx.lu@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/84328 Reviewed-by: Martin L Roth gaumless@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/cpx/Makefile.mk M src/soc/intel/xeon_sp/gnr/Makefile.mk M src/soc/intel/xeon_sp/gnr/soc_acpi.c M src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/lpc_gen1.c A src/soc/intel/xeon_sp/lpc_gen6.c M src/soc/intel/xeon_sp/skx/Makefile.mk M src/soc/intel/xeon_sp/spr/Makefile.mk 8 files changed, 39 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index fca7fe5..a24b50e 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -11,7 +11,7 @@ romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c -ramstage-y += ../chip_gen1.c +ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
diff --git a/src/soc/intel/xeon_sp/gnr/Makefile.mk b/src/soc/intel/xeon_sp/gnr/Makefile.mk index 1618301..9b07408 100644 --- a/src/soc/intel/xeon_sp/gnr/Makefile.mk +++ b/src/soc/intel/xeon_sp/gnr/Makefile.mk @@ -20,7 +20,7 @@ ramstage-y += soc_util.c ramstage-y += ramstage.c ramstage-y += soc_acpi.c -ramstage-y += ../chip_gen6.c +ramstage-y += ../chip_gen6.c ../lpc_gen6.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/gnr/include CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/gnr diff --git a/src/soc/intel/xeon_sp/gnr/soc_acpi.c b/src/soc/intel/xeon_sp/gnr/soc_acpi.c index 54c0cd2..76fabd2 100644 --- a/src/soc/intel/xeon_sp/gnr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/gnr/soc_acpi.c @@ -84,6 +84,9 @@ acpigen_write_name("_PXM"); acpigen_write_integer(device_to_pd(domain));
+ /* _PRT */ + acpigen_write_PRT_pre_routed(domain); + /* _OSC */ acpigen_write_OSC_pci_domain_fixed_caps(domain, get_granted_pcie_features(), diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 7b46564..bf1dedd 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -17,14 +17,6 @@ gen_io_dec[3] = config->gen4_dec; }
-void lpc_soc_init(struct device *dev) -{ - printk(BIOS_SPEW, "pch: lpc_init\n"); - - /* FSP configures IOAPIC and PCHInterrupt Config */ - /* Should read back the ID to fill ACPI IOAPIC accordingly. */ -} - void pch_lpc_soc_fill_io_resources(struct device *dev) { } diff --git a/src/soc/intel/xeon_sp/lpc_gen1.c b/src/soc/intel/xeon_sp/lpc_gen1.c new file mode 100644 index 0000000..9a1c629 --- /dev/null +++ b/src/soc/intel/xeon_sp/lpc_gen1.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <intelblocks/lpc_lib.h> + +void lpc_soc_init(struct device *dev) +{ + printk(BIOS_SPEW, "pch: lpc_init\n"); + + /* FSP configures IOAPIC and PCHInterrupt Config */ + /* Should read back the ID to fill ACPI IOAPIC accordingly. */ +} diff --git a/src/soc/intel/xeon_sp/lpc_gen6.c b/src/soc/intel/xeon_sp/lpc_gen6.c new file mode 100644 index 0000000..d2aaec1 --- /dev/null +++ b/src/soc/intel/xeon_sp/lpc_gen6.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> + +void lpc_soc_init(struct device *dev) +{ + printk(BIOS_SPEW, "pch: lpc_init\n"); + + /* Program irq pin/line for PCI devices by PCH convention */ + pch_pirq_init(); + + /* Explicitly set polarity low for PIRQA to PIRQH */ + for (int i = 0; i < PIRQ_COUNT; i++) { + itss_set_irq_polarity(pcr_read8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + i), 1); + } +} diff --git a/src/soc/intel/xeon_sp/skx/Makefile.mk b/src/soc/intel/xeon_sp/skx/Makefile.mk index 58d783a..456e932 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.mk +++ b/src/soc/intel/xeon_sp/skx/Makefile.mk @@ -16,7 +16,7 @@
ramstage-y += soc_acpi.c ramstage-y += chip.c -ramstage-y += ../chip_gen1.c +ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-y += soc_util.c ramstage-y += cpu.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index 0c4f063..c5f9ece 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -15,7 +15,7 @@
ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c ramstage-y += crashlog.c ioat.c -ramstage-y += ../chip_gen1.c +ramstage-y += ../chip_gen1.c ../lpc_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr
-
Lean Sheng Tan (Code Review)