[XS] Change in coreboot[main]: arch/ppc64: Fix inline assembly for clang

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78446?usp=email )

Change subject: arch/ppc64: Fix inline assembly for clang
......................................................................

arch/ppc64: Fix inline assembly for clang

Use macros from the Linux kernel 6.5 to make the inline assembly also
compile on clang.

TEST: See that the generated code is identical on GCC and compiles on
clang.

Signed-off-by: Arthur Heymans 
Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78446
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Martin L Roth 
---
M src/arch/ppc64/stages.c
1 file changed, 6 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Martin L Roth: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c
index 01b9efa..c6d35ed 100644
--- a/src/arch/ppc64/stages.c
+++ b/src/arch/ppc64/stages.c
@@ -25,10 +25,15 @@
    	_cbmem_top_ptr = stage_arg;

#if ENV_RAMSTAGE
+#define __stringify_in_c(...)	#__VA_ARGS__
+#define stringify_in_c(...)	__stringify_in_c(__VA_ARGS__) " "
+#define PPC_RAW_SLBIA(IH)		(0x7c0003e4 | (((IH) & 0x7) << 21))
+#define PPC_SLBIA(IH)	stringify_in_c(.long PPC_RAW_SLBIA(IH))
+
    hrmor = read_spr(SPR_HRMOR);
    asm volatile("sync; isync" ::: "memory");
    write_spr(SPR_HRMOR, 0);
-	asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory");
+	asm volatile("or 1,1,%0;" PPC_SLBIA(7)"; sync; isync" :: "r"(hrmor) : "memory");
 #endif

main();