[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Nicholas Chin (Code Review)]

Attention is currently required from: Angel Pons, Keith Hui.

Nicholas Chin has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 6:

(1 comment)

Patchset:

PS6:
> I see that the ASM1061 is detected in the PS 4 log. […]

Looks like GPIO 5 is reset by either RSMRST# (pin 101) or SLPS5# (pin 84) depending on the setting in LDN 0xA (ACPI) register 0xE9[5] (default 0=RSMRST#). Calling `system_reset()` `#include <cf9_reset.h>` should cause the PCH to assert PLTRST# which is connected to pin 26 LRESET# on the SuperIO, so GPIO5 should maintain its values after calling that funciton. The SuperIO also buffers the LRESET# signal to those reset outputs on GPIO bank 7, of which RSTOUT2# (pin 77) goes to the PCIe slots.

I guess some logic in `early_init.c` would need to be added to check the configuration of the SuperIO GPIOs and reset the system after changing them, otherwise continue booting if they are already at the desired values.