Chien-Chih Tseng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
WIP: soc/mediatek/mt8192: add apusys init flow
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 4 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc old mode 100644 new mode 100755 index c01d716..0b23296 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -54,6 +54,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += devapc.c ramstage-y += mcupm.c +ramstage-y += apusys.c ramstage-y += soc.c ramstage-y += sspm.c ramstage-y += ufs.c diff --git a/src/soc/mediatek/mt8192/apusys.c b/src/soc/mediatek/mt8192/apusys.c new file mode 100755 index 0000000..605f1c9 --- /dev/null +++ b/src/soc/mediatek/mt8192/apusys.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/apusys.h> +#include <soc/mtlib_common.h> + +#define INFRA2APU_SRAM_PROT_EN (INFRACFG_AO_BASE + 0xe98) +#define APUSYS_MBOX (0x19000000) + +void apusys_init(void) +{ + write32((void *)INFRA2APU_SRAM_PROT_EN, + read32((void *)INFRA2APU_SRAM_PROT_EN) & (~0xc0000000)); + write32((void *)(APUSYS_MBOX + 0x0b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x1b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x2b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x3b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x4b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x5b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x6b0), 0x00010001); + write32((void *)(APUSYS_MBOX + 0x7b0), 0x00010001); + + printk(BIOS_INFO, "INFRA2APU_SRAM_PROT_EN = 0x%x\n", + read32((void *)INFRA2APU_SRAM_PROT_EN)); + printk(BIOS_INFO, "0x190000b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x0b0))); + printk(BIOS_INFO, "0x190001b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x1b0))); + printk(BIOS_INFO, "0x190002b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x2b0))); + printk(BIOS_INFO, "0x190003b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x3b0))); + printk(BIOS_INFO, "0x190004b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x4b0))); + printk(BIOS_INFO, "0x190005b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x5b0))); + printk(BIOS_INFO, "0x190006b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x6b0))); + printk(BIOS_INFO, "0x190007b0 = 0x%x\n", + read32((void *)(APUSYS_MBOX + 0x7b0))); +} diff --git a/src/soc/mediatek/mt8192/include/soc/apusys.h b/src/soc/mediatek/mt8192/include/soc/apusys.h new file mode 100755 index 0000000..389d1e8 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/apusys.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_APUSYS_H +#define SOC_MEDIATEK_MT8192_APUSYS_H + +#include <soc/addressmap.h> +#include <types.h> + +void apusys_init(void); +#endif /* SOC_MEDIATEK_MT8192_APUSYS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c old mode 100644 new mode 100755 index 883f4dc..8c16906 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -4,10 +4,12 @@ #include <soc/devapc.h> #include <soc/emi.h> #include <soc/mcupm.h> +#include <soc/apusys.h> #include <soc/mmu_operations.h> #include <soc/sspm.h> #include <soc/ufs.h> #include <symbols.h> +#include <console/console.h>
static void soc_read_resources(struct device *dev) { @@ -17,6 +19,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + apusys_init(); dapc_init(); mcupm_init(); sspm_init();
Chien-Chih Tseng has removed Patrick Georgi from this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Removed reviewer Patrick Georgi.
Chien-Chih Tseng has removed Martin Roth from this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Removed reviewer Martin Roth.
Chien-Chih Tseng has removed Hung-Te Lin from this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Removed reviewer Hung-Te Lin.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48622
to look at the new patch set (#2).
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
WIP: soc/mediatek/mt8192: add apusys init flow
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 4 files changed, 54 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/2
Chien-Chih Tseng has removed Patrick Georgi from this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Removed reviewer Patrick Georgi.
Chien-Chih Tseng has removed Martin Roth from this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Removed reviewer Martin Roth.
Chien-Chih Tseng has removed Hung-Te Lin from this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Removed reviewer Hung-Te Lin.
flora.fu@mediatek.com has uploaded a new patch set (#3) to the change originally created by Chien-Chih Tseng. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
WIP: soc/mediatek/mt8192: add apusys init flow
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 4 files changed, 54 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/3
flora.fu@mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 3:
Rebase Asurada ToT - Coreboot (Patchset 46)
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48622/4/src/soc/mediatek/mt8192/apu... File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/4/src/soc/mediatek/mt8192/apu... PS4, Line 11: : write32((void *)INFRA2APU_SRAM_PROT_EN, : read32((void *)INFRA2APU_SRAM_PROT_EN) & (~0xc0000000)); I'd encourage using SET32_BITFIELDS API for this, to provide better meaningful names
https://review.coreboot.org/c/coreboot/+/48622/4/src/soc/mediatek/mt8192/apu... PS4, Line 14: write32((void *)(APUSYS_MBOX + 0x0b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x1b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x2b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x3b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x4b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x5b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x6b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x7b0), 0x00010001); : int i;
for (i = 0; i < 8; i++) { /* Explain what is this address pointing at */ SET32_BITFIELDS((void *)(APUSYS_MBOX + i * 0x100 + 0xb0), FIELD1_NAME, 1, FIELD2_NAME, 1); }
Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, flora.fu@mediatek.com,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48622
to look at the new patch set (#5).
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
WIP: soc/mediatek/mt8192: add apusys init flow
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 4 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/5
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 5:
(6 comments)
https://review.coreboot.org/c/coreboot/+/48622/5/src/soc/mediatek/mt8192/apu... File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/5/src/soc/mediatek/mt8192/apu... PS5, Line 24: (u8 *) no need to cast here if you will do (void *) later.
https://review.coreboot.org/c/coreboot/+/48622/5/src/soc/mediatek/mt8192/apu... PS5, Line 24: 0x100 add a comment for name of the regsiter in MBOX + i*0x100 + 0xb0
https://review.coreboot.org/c/coreboot/+/48622/5/src/soc/mediatek/mt8192/apu... PS5, Line 26: SET32_BITFIELDS(addr, : NO_MPU, 1, LOCK, 1); this can be in one line.
https://review.coreboot.org/c/coreboot/+/48622/5/src/soc/mediatek/mt8192/apu... PS5, Line 29: 0x%x %#x
https://review.coreboot.org/c/coreboot/+/48622/5/src/soc/mediatek/mt8192/apu... PS5, Line 29: 0x%x %p (do we support that in coreboot?) or %#x
https://review.coreboot.org/c/coreboot/+/48622/5/src/soc/mediatek/mt8192/apu... PS5, Line 30: APUSYS_MBOX + i * 0x100 + 0xb0 (uintptr_t)addr
Attention is currently required from: Chien-Chih Tseng, Pi-Cheng Chen. flora.fu@mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6: Rebase Asurada ToT - Coreboot (Patchset 50)
Attention is currently required from: Chien-Chih Tseng, Pi-Cheng Chen. flora.fu@mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6: Hi, Hung-Te and coreboot reviewers, The patch is used for developing apu feature and it is not the final proposal, Please just skip the change in your review list. Thanks a lot.
Attention is currently required from: Chien-Chih Tseng, Pi-Cheng Chen. flora.fu@mediatek.com has uploaded a new patch set (#7) to the change originally created by Chien-Chih Tseng. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
WIP: soc/mediatek/mt8192: add apusys init flow
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 4 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/7
Attention is currently required from: Chien-Chih Tseng, Pi-Cheng Chen, flora.fu@mediatek.com. flora.fu@mediatek.com has uploaded a new patch set (#9) to the change originally created by Chien-Chih Tseng. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
soc/mediatek/mt8192: add apusys init flow
Setup APU mbox's functional configuration registers.
BUG=b:186369803 BRANCH=none TEST=boot asurada correctly
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 Signed-off-by: Flora Fu flora.fu@mediatek.com --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 5 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/9
Attention is currently required from: Xi Chen, Pi-Cheng Chen, flora.fu@mediatek.com. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 9:
(1 comment)
File src/soc/mediatek/mt8192/apusys.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118569): https://review.coreboot.org/c/coreboot/+/48622/comment/0d7dbce7_28fdaea8 PS9, Line 37: for (i = 0; i < SIZE_MBOX_FUN; i++) { braces {} are not necessary for single statement blocks
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, flora.fu@mediatek.com. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9: File src/soc/mediatek/mt8192/Makefile.inc has one or more executable bits set in the file permissions. File src/soc/mediatek/mt8192/soc.c has one or more executable bits set in the file permissions.
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, flora.fu@mediatek.com. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 9:
(4 comments)
File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/comment/088601f7_7add9d70 PS9, Line 19: 0x%x %#x
https://review.coreboot.org/c/coreboot/+/48622/comment/a3dccc81_178a2205 PS9, Line 24: 0x%x %#x
File src/soc/mediatek/mt8192/include/soc/apusys.h:
https://review.coreboot.org/c/coreboot/+/48622/comment/c440de9f_10ef1312 PS9, Line 9: (4) 4
https://review.coreboot.org/c/coreboot/+/48622/comment/4d222de6_3b610a69 PS9, Line 23: APU_MBOX_BASE + 0x100, (void *)(APU_MBOX_BASE + 0x100)
and so on for next 2 lines
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, flora.fu@mediatek.com. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 9:
(7 comments)
File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/comment/7f4ac046_d1c63bb3 PS4, Line 11: : write32((void *)INFRA2APU_SRAM_PROT_EN, : read32((void *)INFRA2APU_SRAM_PROT_EN) & (~0xc0000000));
I'd encourage using SET32_BITFIELDS API for this, to provide better meaningful names
Ack
https://review.coreboot.org/c/coreboot/+/48622/comment/3572a81f_3cc086df PS4, Line 14: write32((void *)(APUSYS_MBOX + 0x0b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x1b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x2b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x3b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x4b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x5b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x6b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x7b0), 0x00010001); :
int i; […]
Ack
File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/comment/3a399ddb_35ef6997 PS5, Line 24: (u8 *)
no need to cast here if you will do (void *) later.
Ack
https://review.coreboot.org/c/coreboot/+/48622/comment/8b9a8a8a_da13a1c4 PS5, Line 24: 0x100
add a comment for name of the regsiter in MBOX + i*0x100 + 0xb0
Ack
https://review.coreboot.org/c/coreboot/+/48622/comment/65b5f7a7_7eac3d53 PS5, Line 26: SET32_BITFIELDS(addr, : NO_MPU, 1, LOCK, 1);
this can be in one line.
Ack
https://review.coreboot.org/c/coreboot/+/48622/comment/9461a90c_6bfa9fd0 PS5, Line 29: 0x%x
%p (do we support that in coreboot?) or %#x
Ack
https://review.coreboot.org/c/coreboot/+/48622/comment/0a127603_daf83ec5 PS5, Line 30: APUSYS_MBOX + i * 0x100 + 0xb0
(uintptr_t)addr
Ack
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, flora.fu@mediatek.com. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 9:
(2 comments)
File src/soc/mediatek/mt8192/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48622/comment/3259306a_13cdecd0 PS9, Line 61: ramstage-y += apusys.c Sort these by putting it before
ramstage-y += ../common/auxadc.c
File src/soc/mediatek/mt8192/soc.c:
https://review.coreboot.org/c/coreboot/+/48622/comment/12ea46c7_04b801f4 PS9, Line 7: #include <soc/apusys.h> Sort
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, flora.fu@mediatek.com. flora.fu@mediatek.com has uploaded a new patch set (#10) to the change originally created by Chien-Chih Tseng. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
soc/mediatek/mt8192: add apusys init flow
Setup APU mbox's functional configuration registers.
BUG=b:186369803 BRANCH=none TEST=boot asurada correctly
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 Signed-off-by: Flora Fu flora.fu@mediatek.com --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 5 files changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/10
Attention is currently required from: Hung-Te Lin, Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Yu-Ping Wu. flora.fu@mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 10:
(7 comments)
Patchset:
PS9:
File src/soc/mediatek/mt8192/Makefile. […]
done
File src/soc/mediatek/mt8192/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48622/comment/abe6ddf9_cc1b1d6e PS9, Line 61: ramstage-y += apusys.c
Sort these by putting it before […]
Done
File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/comment/fad57392_d9be734d PS9, Line 19: 0x%x
%#x
Done
https://review.coreboot.org/c/coreboot/+/48622/comment/7b2be742_8634e1f0 PS9, Line 24: 0x%x
%#x
Done
File src/soc/mediatek/mt8192/include/soc/apusys.h:
https://review.coreboot.org/c/coreboot/+/48622/comment/8a7a47c3_00ec380a PS9, Line 9: (4)
4
Done
https://review.coreboot.org/c/coreboot/+/48622/comment/af0fffce_dea92190 PS9, Line 23: APU_MBOX_BASE + 0x100,
(void *)(APU_MBOX_BASE + 0x100) […]
Done
File src/soc/mediatek/mt8192/soc.c:
https://review.coreboot.org/c/coreboot/+/48622/comment/93ace18d_231da33b PS9, Line 7: #include <soc/apusys.h>
Sort
Done
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, Yu-Ping Wu, flora.fu@mediatek.com. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 10: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48622/comment/130dea1e_204ebe14 PS10, Line 12: none asurada
Patchset:
PS10: just some nits
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, Yu-Ping Wu, flora.fu@mediatek.com. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 10:
(1 comment)
File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/comment/2d2d67dc_afc50b31 PS5, Line 29: 0x%x
%#x
Ack
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, Yu-Ping Wu, flora.fu@mediatek.com. flora.fu@mediatek.com has uploaded a new patch set (#11) to the change originally created by Chien-Chih Tseng. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
soc/mediatek/mt8192: add apusys init flow
Setup APU mbox's functional configuration registers.
BUG=b:186369803 BRANCH=asurada TEST=boot asurada correctly
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 Signed-off-by: Flora Fu flora.fu@mediatek.com --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 5 files changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/11
Attention is currently required from: Hung-Te Lin, Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, Yu-Ping Wu. flora.fu@mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48622/comment/93890995_5d7bfb2a PS10, Line 12: none
asurada
Done
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, Yu-Ping Wu, flora.fu@mediatek.com. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 11: Code-Review+2
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, flora.fu@mediatek.com. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 11:
(7 comments)
File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/comment/138c9d86_864f87d4 PS11, Line 19: 0x%p %p
("0x" will be printed with "%p")
https://review.coreboot.org/c/coreboot/+/48622/comment/da1cb01e_a33ed6e3 PS11, Line 20: (void *) Align with BIOS_INFO
https://review.coreboot.org/c/coreboot/+/48622/comment/e4dc33ed_9276e381 PS11, Line 23: SIZE_MBOX_FUN ARRAY_SIZE(mt8192_apu_mbox)
https://review.coreboot.org/c/coreboot/+/48622/comment/6dc6f283_604b511d PS11, Line 24: 0x%p %p
https://review.coreboot.org/c/coreboot/+/48622/comment/8023dda8_edfbdc76 PS11, Line 25: (void *) Align with BIOS_INFO
https://review.coreboot.org/c/coreboot/+/48622/comment/29c43588_43b2912a PS11, Line 37: SIZE_MBOX_FUN ARRAY_SIZE(mt8192_apu_mbox)
File src/soc/mediatek/mt8192/include/soc/apusys.h:
https://review.coreboot.org/c/coreboot/+/48622/comment/54b22b5e_72fc1d38 PS11, Line 9: SIZE_MBOX_FUN Using the ARRAY_SIZE macro, I don't think we need this.
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, flora.fu@mediatek.com. flora.fu@mediatek.com has uploaded a new patch set (#12) to the change originally created by Chien-Chih Tseng. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
soc/mediatek/mt8192: add apusys init flow
Setup APU mbox's functional configuration registers.
BUG=b:186369803 BRANCH=asurada TEST=boot asurada correctly
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 Signed-off-by: Flora Fu flora.fu@mediatek.com --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 5 files changed, 76 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/12
Attention is currently required from: Xi Chen, Pi-Cheng Chen, Rex-BC Chen, flora.fu@mediatek.com. flora.fu@mediatek.com has uploaded a new patch set (#13) to the change originally created by Chien-Chih Tseng. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
soc/mediatek/mt8192: add apusys init flow
Setup APU mbox's functional configuration registers.
BUG=b:186369803 BRANCH=asurada TEST=boot asurada correctly
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 Signed-off-by: Flora Fu flora.fu@mediatek.com --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 5 files changed, 72 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/13
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, Yu-Ping Wu. flora.fu@mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 13:
(7 comments)
File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/comment/d7d5fe4f_79430f02 PS11, Line 19: 0x%p
%p […]
Done
https://review.coreboot.org/c/coreboot/+/48622/comment/cb8ca0bc_58059e3b PS11, Line 20: (void *)
Align with BIOS_INFO
Done
https://review.coreboot.org/c/coreboot/+/48622/comment/a22df845_4781934b PS11, Line 23: SIZE_MBOX_FUN
ARRAY_SIZE(mt8192_apu_mbox)
Done
https://review.coreboot.org/c/coreboot/+/48622/comment/24ac323a_9b563a76 PS11, Line 24: 0x%p
%p
Done
https://review.coreboot.org/c/coreboot/+/48622/comment/5479fbdc_90364625 PS11, Line 25: (void *)
Align with BIOS_INFO
Done
https://review.coreboot.org/c/coreboot/+/48622/comment/5f971d54_7b4a84c5 PS11, Line 37: SIZE_MBOX_FUN
ARRAY_SIZE(mt8192_apu_mbox)
Done
File src/soc/mediatek/mt8192/include/soc/apusys.h:
https://review.coreboot.org/c/coreboot/+/48622/comment/8b875ab5_d2dff3c8 PS11, Line 9: SIZE_MBOX_FUN
Using the ARRAY_SIZE macro, I don't think we need this.
Done
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, flora.fu@mediatek.com. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 13:
(2 comments)
File src/soc/mediatek/mt8192/include/soc/apusys.h:
https://review.coreboot.org/c/coreboot/+/48622/comment/201c10bb_4d418ad9 PS13, Line 19: 4 Don't need this.
https://review.coreboot.org/c/coreboot/+/48622/comment/82ea0e53_b493157f PS13, Line 23: ) Add a trailing comma
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, flora.fu@mediatek.com. flora.fu@mediatek.com has uploaded a new patch set (#14) to the change originally created by Chien-Chih Tseng. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
soc/mediatek/mt8192: add apusys init flow
Setup APU mbox's functional configuration registers.
BUG=b:186369803 BRANCH=asurada TEST=boot asurada correctly
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 Signed-off-by: Flora Fu flora.fu@mediatek.com --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 5 files changed, 72 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48622/14
Attention is currently required from: Xi Chen, Chien-Chih Tseng, Pi-Cheng Chen, Rex-BC Chen, Yu-Ping Wu. flora.fu@mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 14:
(2 comments)
File src/soc/mediatek/mt8192/include/soc/apusys.h:
https://review.coreboot.org/c/coreboot/+/48622/comment/a07cdc22_4913e438 PS13, Line 19: 4
Don't need this.
Done
https://review.coreboot.org/c/coreboot/+/48622/comment/bc55b848_658ef379 PS13, Line 23: )
Add a trailing comma
Done
Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 14: Code-Review+2
Attention is currently required from: Hung-Te Lin, Chien-Chih Tseng. flora.fu@mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 14: Code-Review+1
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: soc/mediatek/mt8192: add apusys init flow ......................................................................
soc/mediatek/mt8192: add apusys init flow
Setup APU mbox's functional configuration registers.
BUG=b:186369803 BRANCH=asurada TEST=boot asurada correctly
Signed-off-by: Chien-Chih Tseng chien-chih.tseng@mediatek.com Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337 Signed-off-by: Flora Fu flora.fu@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48622 Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/apusys.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/apusys.h M src/soc/mediatek/mt8192/soc.c 5 files changed, 72 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved flora.fu@mediatek.com: Looks good to me, but someone else must approve
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 2439417..f69274e 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -42,6 +42,7 @@ romstage-y += ../common/mt6315.c mt6315.c romstage-y += ../common/mt6359p.c mt6359p.c
+ramstage-y += apusys.c ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c diff --git a/src/soc/mediatek/mt8192/apusys.c b/src/soc/mediatek/mt8192/apusys.c new file mode 100644 index 0000000..9e3dfd4 --- /dev/null +++ b/src/soc/mediatek/mt8192/apusys.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/apusys.h> +#include <soc/infracfg.h> + +/* INFRA2APU_SRAM_PROT_EN */ +DEFINE_BITFIELD(PROT_EN, 31, 30) + +/* MBOX Functional Configuration */ +DEFINE_BITFIELD(LOCK, 0, 0) +DEFINE_BITFIELD(NO_MPU, 16, 16) + +static void dump_apusys_reg(void) +{ + int i; + + printk(BIOS_INFO, "INFRA2APU_SRAM_PROT_EN %p = %#x\n", + (void *)&mt8192_infracfg->infra_ao_mm_hang_free, + read32(&mt8192_infracfg->infra_ao_mm_hang_free)); + + for (i = 0; i < ARRAY_SIZE(mt8192_apu_mbox); i++) { + printk(BIOS_INFO, "APU_MBOX %p = %#x\n", + (void *)&mt8192_apu_mbox[i]->mbox_func_cfg, + read32(&mt8192_apu_mbox[i]->mbox_func_cfg)); + } +} + +void apusys_init(void) +{ + int i; + + SET32_BITFIELDS(&mt8192_infracfg->infra_ao_mm_hang_free, PROT_EN, 0); + + /* Setup MBOX MPU for non secure access */ + for (i = 0; i < ARRAY_SIZE(mt8192_apu_mbox); i++) + SET32_BITFIELDS(&mt8192_apu_mbox[i]->mbox_func_cfg, NO_MPU, 1, LOCK, 1); + + dump_apusys_reg(); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 51a89e1..8dd76d9 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -87,6 +87,7 @@ DISP_POSTMASK0_BASE = IO_PHYS + 0x0400D000, DISP_DITHER0_BASE = IO_PHYS + 0x0400E000, DSI0_BASE = IO_PHYS + 0x04010000, + APU_MBOX_BASE = IO_PHYS + 0x09000000, };
#endif diff --git a/src/soc/mediatek/mt8192/include/soc/apusys.h b/src/soc/mediatek/mt8192/include/soc/apusys.h new file mode 100644 index 0000000..9a7e926 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/apusys.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_APUSYS_H +#define SOC_MEDIATEK_MT8192_APUSYS_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_apu_mbox_regs { + u32 mbox_in[8]; + u32 mbox_out[8]; + u32 mbox_reserved1[28]; + u32 mbox_func_cfg; + u32 mbox0_reserved2[19]; +}; + +check_member(mt8192_apu_mbox_regs, mbox_func_cfg, 0x0b0); + +static struct mt8192_apu_mbox_regs * const mt8192_apu_mbox[] = { + (void *)APU_MBOX_BASE, + (void *)(APU_MBOX_BASE + 0x100), + (void *)(APU_MBOX_BASE + 0x500), + (void *)(APU_MBOX_BASE + 0x600), +}; + +void apusys_init(void); +#endif /* SOC_MEDIATEK_MT8192_APUSYS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 883f4dc..70c5fa3 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h> +#include <soc/apusys.h> #include <soc/devapc.h> #include <soc/emi.h> #include <soc/mcupm.h> @@ -17,6 +18,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + apusys_init(); dapc_init(); mcupm_init(); sspm_init();