[M] Change in coreboot[main]: mb/google/corsola: Add audio codec ALC5650 for Chinchou Devbeep

[Yang Wu (Code Review)]

Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email )

Change subject: mb/google/corsola: Add audio codec ALC5650 for Chinchou Devbeep
......................................................................

mb/google/corsola: Add audio codec ALC5650 for Chinchou Devbeep

BUG=b:305828247
TEST=Verify Devbeep at Depthcharge console

Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854
Signed-off-by: wuyang5 
---
M src/mainboard/google/corsola/mainboard.c
M src/soc/mediatek/mt8186/include/soc/pll.h
M src/soc/mediatek/mt8186/pll.c
3 files changed, 64 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79064/1

diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c
index b2c65eb..8ba5ae3 100644
--- a/src/mainboard/google/corsola/mainboard.c
+++ b/src/mainboard/google/corsola/mainboard.c
@@ -2,10 +2,13 @@

#include <bootmode.h>
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <gpio.h>
 #include <soc/bl31.h>
+#include <soc/i2c.h>
 #include <soc/msdc.h>
+#include <soc/pll.h>
 #include <soc/spm.h>
 #include <soc/usb.h>

@@ -23,6 +26,23 @@
    gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_I2S3_DO);
 }

+static void configure_audio_ALC5645(void)
+{
+	mtcmos_audio_power_on();
+
+	/* Set up I2S */
+	gpio_set_mode(GPIO(I2S1_MCK), PAD_I2S1_MCK_FUNC_I2S1_MCK);
+	gpio_set_mode(GPIO(I2S1_BCK), PAD_I2S1_BCK_FUNC_I2S1_BCK);
+	gpio_set_mode(GPIO(I2S1_LRCK), PAD_I2S1_LRCK_FUNC_I2S1_LRCK);
+	gpio_set_mode(GPIO(I2S1_DO), PAD_I2S1_DO_FUNC_I2S1_DO);
+
+	/* Init i2c bus Timing register for audio codecs */
+	mtk_i2c_bus_init(5, I2C_SPEED_STANDARD);
+
+	/* set I2S clock to 48KHz */
+	mt_pll_set_aud_div(48 * KHz);
+}
+
 static void mainboard_init(struct device *dev)
 {
    mtk_msdc_configure_emmc(true);
@@ -36,7 +56,10 @@

setup_usb_host();

-	configure_audio();
+	if (CONFIG(BOARD_GOOGLE_CHINCHOU))
+		configure_audio_ALC5645();
+	else
+		configure_audio();

if (spm_init())
    	printk(BIOS_ERR, "spm init failed, system suspend may not work\n");
@@ -67,3 +90,4 @@
 struct chip_operations mainboard_ops = {
    .enable_dev = mainboard_enable,
 };
+
diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h
index 8df7f96..0fd0e1c 100644
--- a/src/soc/mediatek/mt8186/include/soc/pll.h
+++ b/src/soc/mediatek/mt8186/include/soc/pll.h
@@ -8,6 +8,7 @@
 #ifndef SOC_MEDIATEK_MT8186_PLL_H
 #define SOC_MEDIATEK_MT8186_PLL_H

+#include <assert.h>
 #include <device/mmio.h>
 #include <types.h>
 #include <soc/pll_common.h>
@@ -495,6 +496,8 @@
 enum {
    CLK26M_HZ	= 26 * MHz,
    MAINPLL_D5_HZ = MAINPLL_HZ / 5,
+	APLL1_CK_HZ	= APLL1_HZ,
+	APLL2_CK_HZ	= APLL2_HZ,
 };

/* top_mux rate */
@@ -526,4 +529,5 @@

DEFINE_BITFIELD(USB_TOP_CFG_MACRO_CTRL, 1, 0)

+void mt_pll_set_aud_div(u32 rate);
 #endif /* SOC_MEDIATEK_MT8186_PLL_H */
diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c
index a6165ef..3368610 100644
--- a/src/soc/mediatek/mt8186/pll.c
+++ b/src/soc/mediatek/mt8186/pll.c
@@ -587,3 +587,38 @@

return 0;
 }
+
+void mt_pll_set_aud_div(u32 rate)
+{
+	u32 mclk_div;
+	u32 apll_clock = APLL2_CK_HZ;
+	int apll1 = 0;
+
+	if (rate % 11025 == 0) {
+		/* use APLL1 instead */
+		apll1 = 1;
+		apll_clock = APLL1_CK_HZ;
+	}
+	/* I2S1 clock */
+	mclk_div = (apll_clock / 256 / rate) - 1;
+	assert(apll_clock == rate * 256 * (mclk_div + 1));
+
+	if (apll1) {
+		/* mclk */
+		clrbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
+		clrsetbits32(&mtk_topckgen->clk_auddiv_1, 0xff << 8,
+			     mclk_div << 8);
+		/* bclk */
+		clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 24,
+			     7 << 24);
+	} else {
+		/* mclk */
+		setbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
+		clrsetbits32(&mtk_topckgen->clk_auddiv_2, 0xff << 8,
+			     mclk_div << 8);
+		/* bclk */
+		clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 28,
+			     7 << 28);
+	}
+}
+