David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43060 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL: 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E
BUG=b:159195585,b:152936481,b:156435028 TEST=build.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1 --- M src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt M util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt 2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43060/1
diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt index 49fe445..f57b372 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt @@ -11,3 +11,5 @@ MT53E512M32D2NP-046 WT:E,spd-1.hex H9HCNNNCPMMLXR-NEE,spd-3.hex K4UBE3D4AA-MGCR,spd-3.hex +MT53E512M64D4NW-046 WT:E,spd-1.hex +MT53E1G64D8NW-046 WT:E,spd-3.hex diff --git a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt index b9dd4b3..109fadb 100644 --- a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt @@ -157,6 +157,30 @@ "ranksPerChannel": 2, "speedMbps": 4267 } + }, + { + "name": "MT53E512M64D4NW-046 WT:E", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + }, + { + "name": "MT53E1G64D8NW-046 WT:E", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 4267 + } } ] }
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43060 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 1: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43060 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 1: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43060 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
Patch Set 1: Code-Review+2
Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43060 )
Change subject: lp4x: Add new memory parts and generate SPDs ......................................................................
lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL: 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E
BUG=b:159195585,b:152936481,b:156435028 TEST=build.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Zhuohao Lee zhuohao@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt M util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt 2 files changed, 26 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Zhuohao Lee: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt index 49fe445..f57b372 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt @@ -11,3 +11,5 @@ MT53E512M32D2NP-046 WT:E,spd-1.hex H9HCNNNCPMMLXR-NEE,spd-3.hex K4UBE3D4AA-MGCR,spd-3.hex +MT53E512M64D4NW-046 WT:E,spd-1.hex +MT53E1G64D8NW-046 WT:E,spd-3.hex diff --git a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt index b9dd4b3..109fadb 100644 --- a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt @@ -157,6 +157,30 @@ "ranksPerChannel": 2, "speedMbps": 4267 } + }, + { + "name": "MT53E512M64D4NW-046 WT:E", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + }, + { + "name": "MT53E1G64D8NW-046 WT:E", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 4267 + } } ] }