Patch merged into coreboot/master: c6313db baytrail: Enable PCIe common clock and ASPM

the following patch was just integrated into master:
commit c6313db34f26bcb8bdbb5ff04ebc9c9e7193cf0f
Author: Duncan Laurie 
Date:   Thu Jan 16 11:18:36 2014 -0800

baytrail: Enable PCIe common clock and ASPM

Enable the config options to have the device enumeration layer configure
    common clock and ASPM for endpoints.

BUG=chrome-os-partner:23629
    BRANCH=baytrail
    TEST=build and boot on rambi, check PCIe for ASPM and common clock:

lspci -vv -s 0:1c.0 | grep LnkCtl:
     LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+

lspci -vv -s 1:00.0 | grep LnkCtl:
     LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+

Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f
    Signed-off-by: Duncan Laurie 
    Reviewed-on: https://chromium-review.googlesource.com/182860
    Reviewed-by: Aaron Durbin 
    Signed-off-by: Aaron Durbin 
    Reviewed-on: http://review.coreboot.org/5051
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel 
    Reviewed-by: Patrick Georgi

See http://review.coreboot.org/5051 for details.

-gerrit