Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46262 )
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/variants: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
BUG=b:160996445 TEST=TODO: only tested on volteer, needs test on real hardware
Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/mainboard/google/volteer/variants/delbin/gpio.c M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 4 files changed, 26 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46262/1
diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c index 5748bb3..bebf38f 100644 --- a/src/mainboard/google/volteer/variants/delbin/gpio.c +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -27,8 +27,8 @@ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
- /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 21b1f07..ef52517 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -59,6 +59,14 @@ device i2c 15 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "clock_pin" = "0" + device pci 00.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 1ccdb87..7f806ea 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -126,6 +126,14 @@ device i2c 15 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "clock_pin" = "0" + device pci 00.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 8ce6875..7528a4f 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -182,6 +182,14 @@ device i2c 15 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "clock_pin" = "0" + device pci 00.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46262
to look at the new patch set (#5).
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/variants: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
BUG=b:160996445 TEST=TODO: only tested on volteer, needs test on real hardware
Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/mainboard/google/volteer/variants/delbin/gpio.c M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 4 files changed, 26 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46262/5
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46262
to look at the new patch set (#10).
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/variants: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
BUG=b:160996445 TEST=TODO: only tested on volteer, needs test on real hardware
Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/mainboard/google/volteer/variants/delbin/gpio.c M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 4 files changed, 26 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46262/10
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46262
to look at the new patch set (#11).
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/variants: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
BUG=b:160996445 TEST=TODO: only tested on volteer, needs test on real hardware
Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 3 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46262/11
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46262
to look at the new patch set (#12).
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/variants: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
BUG=b:160996445 TEST=tested on delbin
Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 4 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46262/12
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46262 )
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46262/13/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/delbin/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46262/13/src/mainboard/google/volte... PS13, Line 155: register "clock_pin" = "0" this is redundant
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46262 )
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46262/13/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/delbin/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46262/13/src/mainboard/google/volte... PS13, Line 155: register "clock_pin" = "0"
this is redundant
or a macro would be more descriptive, e.g. #define PCIE_SRCCLK_0 0 etc.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46262
to look at the new patch set (#14).
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/variants: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state.
BUG=b:160996445 TEST=tested on delbin
Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/mainboard/google/volteer/variants/delbin/gpio.c M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 6 files changed, 36 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46262/14
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46262 )
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46262/13/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/delbin/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46262/13/src/mainboard/google/volte... PS13, Line 155: register "clock_pin" = "0"
or a macro would be more descriptive, e.g. […]
I thought about adding an enum, but the reality is the limit is very SOC specific and it just maps to integers and I don't think rtd3 driver is the right place to define it. (I think we should eventually extract the PCIe UPDs into a common struct and define it there)
I left this one as 0 because although it is redundant it is making it clear that this maps to pin 0.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46262 )
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
Patch Set 15: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46262 )
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
Patch Set 15: Code-Review+2
Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46262 )
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
mb/google/volteer/variants: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state.
BUG=b:160996445 TEST=tested on delbin
Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie dlaurie@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46262 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/delbin/gpio.c M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 6 files changed, 36 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c index 5748bb3..bebf38f 100644 --- a/src/mainboard/google/volteer/variants/delbin/gpio.c +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -27,8 +27,8 @@ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
- /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 5b9caa0..bd4bf80 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -148,6 +148,14 @@ device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index caedfda..87959b8 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -179,6 +179,14 @@ device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 069b2f0..5c10ec5 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -29,6 +29,8 @@ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+ /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B3 : CPU_GP2 ==> PEN_DET_ODL */ PAD_CFG_GPI(GPP_B3, NONE, DEEP), /* B5 : ISH_I2C0_CVF_SDA */ diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 72cb79a..a1012a6 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -281,6 +281,14 @@ device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d2b1354..cdbde98 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -194,6 +194,14 @@ device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy.
-
Duncan Laurie (Code Review) -
Furquan Shaikh (Code Review)
-
Tim Wawrzynczak (Code Review)