Change in coreboot[master]: soc/amd/picasso: fix MCACHE on psp_verstage RO boot

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54711 )

Change subject: soc/amd/picasso: fix MCACHE on psp_verstage RO boot
......................................................................

soc/amd/picasso: fix MCACHE on psp_verstage RO boot

On RW boot path psp_verstage call cbfs_map which calls chain of
_cbfs_alloc, cbfs_boot_lookup and cbfs_get_boot_device. Then
cbfs_get_boot_device initializes MCACHE which is used later.

However on RO boot path psp_verstage doesn't try to find anything in the
CBFS which results RO MCACHE not to be initialized. Add
cbfs_get_boot_device(true) to explicitly initialize MCACHE on recovery
boot.

BUG=b:177091575
BRANCH=none
TEST=build and boot jelboz

Signed-off-by: Kangheui Won 
Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54711
Reviewed-by: Julius Werner 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/common/psp_verstage/psp_verstage.c
M src/soc/amd/picasso/Kconfig
2 files changed, 10 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved

diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c
index 2265e17..5c59c4f 100644
--- a/src/soc/amd/common/psp_verstage/psp_verstage.c
+++ b/src/soc/amd/common/psp_verstage/psp_verstage.c
@@ -238,6 +238,16 @@
    	reboot_into_recovery(ctx, retval);

post_code(POSTCODE_UPDATE_BOOT_REGION);
+
+	/*
+	 * Since psp_verstage doesn't load next stage we never call
+	 * any cbfs API on RO path. However we still need to initialize
+	 * RO CBFS MCACHE manually to pass it in transfer_buffer.
+	 * In RW path, MCACHE build will be skipped for RO region since
+	 * we already built here.
+	 */
+	cbfs_get_boot_device(true);
+
    retval = update_boot_region(ctx);
    if (retval)
    	reboot_into_recovery(ctx, retval);
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index b930277..4bfd093 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -67,7 +67,6 @@
    select FSP_COMPRESS_FSP_S_LZMA
    select UDK_2017_BINDING
    select HAVE_CF9_RESET
-	select NO_CBFS_MCACHE if VBOOT_STARTS_BEFORE_BOOTBLOCK

config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
    default 3200