HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41676 )
Change subject: src: Remove duplicated includes ......................................................................
src: Remove duplicated includes
Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/51nb/x210/romstage.c M src/mainboard/google/fizz/mainboard.c M src/soc/amd/common/block/acpi/acpi.c M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/intel/braswell/northcluster.c M src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/i2c.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/early_setup.c 9 files changed, 0 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/41676/1
diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index caaa52d..60f008c 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <string.h> #include <assert.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index c86be82..7b89058 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -10,7 +10,6 @@ #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <intelblocks/power_limit.h> -#include <variant/gpio.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/pci_devs.h> diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 964aef1..2be9b9e 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -10,7 +10,6 @@ #include <halt.h> #include <security/vboot/vboot_common.h> #include <soc/southbridge.h> -#include <halt.h>
void poweroff(void) { diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index d2a65c8..eb129dc 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -12,7 +12,6 @@
/* The LPC-ISA bridge is always at D14F3 */ #if !defined(__SIMPLE_DEVICE__) -#include <device/device.h> #define _LPCB_DEV pcidev_on_root(0x14, 0x3) #else #define _LPCB_DEV PCI_DEV(0, 0x14, 0x3) diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 67f8649..bf922c4 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -7,7 +7,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/lapic_def.h> -#include <cpu/x86/smm.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/iosf.h> diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 73dacef..2505bbc 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h> -#include <device/mmio.h> #include <console/console.h> #include <device/mmio.h> #include <delay.h> diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index af2e029..f80fb97 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -7,9 +7,7 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/i2c.h> -#include <device/mmio.h> #include <soc/pll.h> -#include <soc/i2c.h>
#define I2C_CLK_HZ (AXI_HZ / 16)
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 63d2b81..4864945 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -7,7 +7,6 @@ #include <amdblocks/acpimmio.h> #include <device/pci_ops.h> #include <console/console.h> -#include <amdblocks/acpimmio.h>
#include "hudson.h"
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 09a2750..8bca42b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -9,7 +9,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> -#include <amdblocks/acpimmio.h>
#include "hudson.h" #include "pci_devs.h"
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41676 )
Change subject: src: Remove duplicated includes ......................................................................
Patch Set 1:
(10 comments)
https://review.coreboot.org/c/coreboot/+/41676/1/src/mainboard/51nb/x210/rom... File src/mainboard/51nb/x210/romstage.c:
https://review.coreboot.org/c/coreboot/+/41676/1/src/mainboard/51nb/x210/rom... PS1, Line 8: #include <string.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/1/src/mainboard/google/fizz/m... File src/mainboard/google/fizz/mainboard.c:
https://review.coreboot.org/c/coreboot/+/41676/1/src/mainboard/google/fizz/m... PS1, Line 22: <variant/gpio.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/amd/common/block/ac... File src/soc/amd/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/amd/common/block/ac... PS1, Line 10: <halt.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/amd/common/block/lp... File src/soc/amd/common/block/lpc/lpc_util.c:
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/amd/common/block/lp... PS1, Line 5: <device/device.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/intel/braswell/nort... File src/soc/intel/braswell/northcluster.c:
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/intel/braswell/nort... PS1, Line 5: cpu/x86/smm.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/mediatek/common/dsi... PS1, Line 6: <device/mmio.h duplicated
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/mediatek/mt8173/i2c... File src/soc/mediatek/mt8173/i2c.c:
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/mediatek/mt8173/i2c... PS1, Line 7: device/mmio.h duplicated
https://review.coreboot.org/c/coreboot/+/41676/1/src/soc/mediatek/mt8173/i2c... PS1, Line 9: soc/i2c.h duplicated
https://review.coreboot.org/c/coreboot/+/41676/1/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/41676/1/src/southbridge/amd/agesa/h... PS1, Line 7: amdblocks/acpimmio.h duplicated
https://review.coreboot.org/c/coreboot/+/41676/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/41676/1/src/southbridge/amd/pi/huds... PS1, Line 8: amdblocks/acpimmio.h duplicated
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41676 )
Change subject: src: Remove duplicated includes ......................................................................
Patch Set 2:
(10 comments)
I've added some comments to make the review easy ...
Thank you
https://review.coreboot.org/c/coreboot/+/41676/2/src/mainboard/51nb/x210/rom... File src/mainboard/51nb/x210/romstage.c:
https://review.coreboot.org/c/coreboot/+/41676/2/src/mainboard/51nb/x210/rom... PS2, Line 8: #include <string.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/2/src/mainboard/google/fizz/m... File src/mainboard/google/fizz/mainboard.c:
https://review.coreboot.org/c/coreboot/+/41676/2/src/mainboard/google/fizz/m... PS2, Line 22: include <variant/gpio.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/amd/common/block/ac... File src/soc/amd/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/amd/common/block/ac... PS2, Line 10: #include <halt.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/amd/common/block/lp... File src/soc/amd/common/block/lpc/lpc_util.c:
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/amd/common/block/lp... PS2, Line 5: #include <device/device.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/intel/braswell/nort... File src/soc/intel/braswell/northcluster.c:
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/intel/braswell/nort... PS2, Line 5: #include <cpu/x86/smm.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/mediatek/common/dsi... File src/soc/mediatek/common/dsi.c:
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/mediatek/common/dsi... PS2, Line 6: #include <device/mmio.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/mediatek/mt8173/i2c... File src/soc/mediatek/mt8173/i2c.c:
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/mediatek/mt8173/i2c... PS2, Line 7: #include <device/mmio.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/2/src/soc/mediatek/mt8173/i2c... PS2, Line 9: include <soc/i2c.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/2/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/41676/2/src/southbridge/amd/agesa/h... PS2, Line 7: #include <amdblocks/acpimmio.h> duplicated
https://review.coreboot.org/c/coreboot/+/41676/2/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/41676/2/src/southbridge/amd/pi/huds... PS2, Line 8: #include <amdblocks/acpimmio.h> duplicated
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41676 )
Change subject: src: Remove duplicated includes ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41676 )
Change subject: src: Remove duplicated includes ......................................................................
src: Remove duplicated includes
Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/41676 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/51nb/x210/romstage.c M src/mainboard/google/fizz/mainboard.c M src/soc/amd/common/block/acpi/acpi.c M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/intel/braswell/northcluster.c M src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/i2c.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/early_setup.c 9 files changed, 0 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index caaa52d..60f008c 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <string.h> #include <assert.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index c86be82..7b89058 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -10,7 +10,6 @@ #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <intelblocks/power_limit.h> -#include <variant/gpio.h> #include <smbios.h> #include <soc/gpio.h> #include <soc/pci_devs.h> diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 964aef1..2be9b9e 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -10,7 +10,6 @@ #include <halt.h> #include <security/vboot/vboot_common.h> #include <soc/southbridge.h> -#include <halt.h>
void poweroff(void) { diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index d2a65c8..eb129dc 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -12,7 +12,6 @@
/* The LPC-ISA bridge is always at D14F3 */ #if !defined(__SIMPLE_DEVICE__) -#include <device/device.h> #define _LPCB_DEV pcidev_on_root(0x14, 0x3) #else #define _LPCB_DEV PCI_DEV(0, 0x14, 0x3) diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index dd49acd..1f310d4 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -7,7 +7,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/lapic_def.h> -#include <cpu/x86/smm.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/iosf.h> diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 73dacef..2505bbc 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h> -#include <device/mmio.h> #include <console/console.h> #include <device/mmio.h> #include <delay.h> diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index af2e029..f80fb97 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -7,9 +7,7 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/i2c.h> -#include <device/mmio.h> #include <soc/pll.h> -#include <soc/i2c.h>
#define I2C_CLK_HZ (AXI_HZ / 16)
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 63d2b81..4864945 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -7,7 +7,6 @@ #include <amdblocks/acpimmio.h> #include <device/pci_ops.h> #include <console/console.h> -#include <amdblocks/acpimmio.h>
#include "hudson.h"
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 09a2750..8bca42b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -9,7 +9,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> -#include <amdblocks/acpimmio.h>
#include "hudson.h" #include "pci_devs.h"
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41676 )
Change subject: src: Remove duplicated includes ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4604 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4603 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4602 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4601
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)