Attention is currently required from: Martin Roth. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52586 )
Change subject: util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config ......................................................................
Patch Set 2:
(1 comment)
File util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt:
https://review.coreboot.org/c/coreboot/+/52586/comment/13556234_d1273dec PS2, Line 71: "ranksPerChannel": 1,
whoops, I think this can calculated by diesPerPackage
Eric, you are correct that this is 2 ranks per channel. Channels across die0 and die1 share the same DQ/DQS pins but use a separate CS line. Example: DQ[15:0]_A/DQS[1:0]_*_A are shared between Channel A of die 0 (ZQ0) and Channel A of die 1 (ZQ1) and they use separate CS lines CS0_A and CS1_A to select the appropriate die. So, ranksPerChannel here is 2.
Can you please push a fix for this?
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Furquan Shaikh (Code Review)