Lee Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16001
-gerrit
commit bfa31649a4008d82594655976f089fbce18ba17f Author: Lee Leahy leroy.p.leahy@intel.com Date: Sun Jul 31 11:53:28 2016 -0700
arch/x86: Enable postcar console
dd a Kconfig value to enable the console during postcar. Add a call to console_init at the beginning of the postcar stage in exit_car.S.
TEST=Build and run on Galileo Gen2
Change-Id: I66e2ec83344129ede2c7d6e5627c8062e28f50ad Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/arch/x86/Kconfig | 7 +++++++ src/arch/x86/exit_car.S | 5 +++++ 2 files changed, 12 insertions(+)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index af73a58..ed32461 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -194,6 +194,13 @@ config VERSTAGE_ADDR config POSTCAR_STAGE def_bool n
+config POSTCAR_CONSOLE + bool "Enable console output during postcar." + depends on POSTCAR_STAGE + default n + help + Use console during the postcar if supported + config VERSTAGE_DEBUG_SPINLOOP bool default n diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index a51d662..13c2390 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -26,6 +26,11 @@ stack_top: .text .global _start _start: +#if IS_ENABLED(CONFIG_POSTCAR_CONSOLE) + /* Enable the console */ + call console_init +#endif /* CONFIG_POSTCAR_CONSOLE */ + /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car
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Lee Leahy