Change in coreboot[master]: mb/google/dedede: Add PCIe Root Port Configuration

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39166 )

Change subject: mb/google/dedede: Add PCIe Root Port Configuration
......................................................................

mb/google/dedede: Add PCIe Root Port Configuration

Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian 
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39166/1

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index d5f58ba..bbd7642 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -76,6 +76,30 @@
    	[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
    }"

+	# PCIE Root Port Configuration
+	register "PcieRpEnable[0]" = "0"
+	register "PcieRpEnable[1]" = "0"
+	register "PcieRpEnable[2]" = "0"
+	register "PcieRpEnable[3]" = "0"
+	register "PcieRpEnable[4]" = "0"
+	register "PcieRpEnable[5]" = "0"
+	register "PcieRpEnable[6]" = "0"
+	register "PcieRpEnable[7]" = "0"
+
+	register "PcieClkSrcUsage[0]" = "0xff"
+	register "PcieClkSrcUsage[1]" = "0xff"
+	register "PcieClkSrcUsage[2]" = "0xff"
+	register "PcieClkSrcUsage[3]" = "0xff"
+	register "PcieClkSrcUsage[4]" = "0xff"
+	register "PcieClkSrcUsage[5]" = "0xff"
+
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "0"
+	register "PcieClkSrcClkReq[2]" = "0"
+	register "PcieClkSrcClkReq[3]" = "0"
+	register "PcieClkSrcClkReq[4]" = "0"
+	register "PcieClkSrcClkReq[5]" = "0"
+
    # Enable EMMC HS400 mode
    register "ScsEmmcHs400Enabled" = "1"

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39166 )

Change subject: mb/google/dedede: Add PCIe Root Port Configuration
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39166/1/src/mainboard/google/dedede... 
File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/39166/1/src/mainboard/google/dedede... 
PS1, Line 96: "PcieClkSrcClkReq[0]" = "0"
Aamir@: Should it be 0 or 0xff here?

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39166 )

Change subject: mb/google/dedede: Add PCIe Root Port Configuration
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39166/1/src/mainboard/google/dedede... 
File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/39166/1/src/mainboard/google/dedede... 
PS1, Line 96: "PcieClkSrcClkReq[0]" = "0"
> Aamir@: Should it be 0 or 0xff here?

register "PcieClkSrcClkReq[0]" = "0"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5"

This would be invalidated based on unused PcieClkSrcUsage.

[Karthik Ramasubramanian (Code Review)]

Hello Varshit B Pandya, build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Tim Wawrzynczak, Aamir Bohra,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39166

to look at the new patch set (#3).

Change subject: mb/google/dedede: Add PCIe Root Port Configuration
......................................................................

mb/google/dedede: Add PCIe Root Port Configuration

Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian 
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39166/3

[Karthik Ramasubramanian (Code Review)]

Hello Varshit B Pandya, build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Tim Wawrzynczak, Aamir Bohra,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39166

to look at the new patch set (#4).

Change subject: mb/google/dedede: Add PCIe Root Port Configuration
......................................................................

mb/google/dedede: Add PCIe Root Port Configuration

Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian 
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39166/4

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39166 )

Change subject: mb/google/dedede: Add PCIe Root Port Configuration
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39166/1/src/mainboard/google/dedede... 
File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/39166/1/src/mainboard/google/dedede... 
PS1, Line 96: "PcieClkSrcClkReq[0]" = "0"
> register "PcieClkSrcClkReq[0]" = "0" […]

Done

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39166 )

Change subject: mb/google/dedede: Add PCIe Root Port Configuration
......................................................................

Patch Set 7: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39166 )

Change subject: mb/google/dedede: Add PCIe Root Port Configuration
......................................................................

mb/google/dedede: Add PCIe Root Port Configuration

Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian 
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 25 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index d5f58ba..0efb76d 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -76,6 +76,31 @@
    	[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
    }"

+	# PCIE Root Port Configuration
+	register "PcieRpEnable[0]" = "0"
+	register "PcieRpEnable[1]" = "0"
+	register "PcieRpEnable[2]" = "0"
+	register "PcieRpEnable[3]" = "0"
+	register "PcieRpEnable[4]" = "0"
+	register "PcieRpEnable[5]" = "0"
+	register "PcieRpEnable[6]" = "0"
+	register "PcieRpEnable[7]" = "0"
+
+	register "PcieClkSrcUsage[0]" = "0xff"
+	register "PcieClkSrcUsage[1]" = "0xff"
+	register "PcieClkSrcUsage[2]" = "0xff"
+	register "PcieClkSrcUsage[3]" = "0xff"
+	register "PcieClkSrcUsage[4]" = "0xff"
+	register "PcieClkSrcUsage[5]" = "0xff"
+
+	# PCIE Clock Request to Clock Source Mapping
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+
    # Enable EMMC HS400 mode
    register "ScsEmmcHs400Enabled" = "1"