Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Sridhar Siricilla, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61431 )
Change subject: soc/intel/common/cse: Rework heci_disable function ......................................................................
Patch Set 4:
(6 comments)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/61431/comment/870fabac_46e5921a PS3, Line 22: only done
nit: only be done
Ack
https://review.coreboot.org/c/coreboot/+/61431/comment/ca35c12a_1e58d30e PS3, Line 22: From CNL PCH onwards,`HECI1` disabling can only done using : non-posted sideband write after FSP-S sets the postboot_sai : attribute. : Use this config to include common CSE block to make : HECI function disable in SMM mod
Reordering of statements may require, something like below.. […]
Ack
https://review.coreboot.org/c/coreboot/+/61431/comment/cad78f5b_2526f2fa PS3, Line 25: make : HECI
nit: make the HECI function in the SMM mode
You mean HECI function *disable* in the SMM mode.
https://review.coreboot.org/c/coreboot/+/61431/comment/c1150470_b294c16b PS3, Line 43: Prior to postboot_sai enforcement since CNL PCH, `HECI1` device were : disable using private configuration register (PCR) write.
This mechanism is available starting from CNL PCH. […]
Ack
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/61431/comment/55063aca_9e30389c PS3, Line 493: PCR
PCR.
Ack
https://review.coreboot.org/c/coreboot/+/61431/comment/adf103f3_74f31a70 PS3, Line 494: PSF port id for disabling cse is expected to be different between : * SoC generation hence, allow SoC to implement the override.
It may need rephrasing...
Ack
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Subrata Banik (Code Review)