[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Expend EC share memory register defi...

[Tim Van Patten (Code Review)]

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Tim Wawrzynczak, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian.

Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68077 )

Change subject: mb/google/skyrim/var/winterhold: Expend EC share memory register define for Dynamic Thermal Table Switching Proposal
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Patch Set 2:

(5 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/68077/comment/b4d33a8f_4a0ff24e 
PS2, Line 7: mb/google/skyrim/var/winterhold: Expend EC share memory
           : register define for Dynamic Thermal Table Switching Proposal
ec/google/chromeec/acpi/ec: Add STTT, STTB

https://review.coreboot.org/c/coreboot/+/68077/comment/b059d3d4_939f6661 
PS2, Line 10: Define offset 0x09 bit 5 for temperature status of thermal
            : table switch
nit: Add "STTT", to clarify which this is.

https://review.coreboot.org/c/coreboot/+/68077/comment/6bf013c8_03289599 
PS2, Line 12: Define offset 0x09 bit 6 for body detection status of thermal
            : table switch
Same. Add "STTB".

File src/ec/google/chromeec/acpi/ec.asl:

https://review.coreboot.org/c/coreboot/+/68077/comment/f061b7db_9906226e 
PS2, Line 59: 		RSV1, 1,	// Reserved bit
Why is 1 bit being reserved?   Why can't these be bits 4 and 5?

https://review.coreboot.org/c/coreboot/+/68077/comment/315ab149_a5c57cc4 
PS2, Line 61:     
whitespace: use tab here