Change in ...coreboot[master]: mb/google/sarien: Configure both GPP_A13 and GPP_15 for SSD on Arcada
Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32361
Change subject: mb/google/sarien: Configure both GPP_A13 and GPP_15 for SSD on Arcada ......................................................................
mb/google/sarien: Configure both GPP_A13 and GPP_15 for SSD on Arcada
Currently, Arcada only supports D3hot during S0iX and there is a power leakage around 5~10mW depending on SSD vendors. To support D3cold for SSD during S0iX, one MOSFET(U6310) will be added on DVT2 and two GPIOs are required to be configured. GPP_A13 is to control SSD_SCP_PWR_EN(power enable) and GPP_A13 is to control SSD reset.
BUG=b:130741066 TEST=Measure both SSD power and platform power during S0iX from Arcada
Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50 Signed-off-by: Roy Mingi Park roy.mingi.park@intel.com --- M src/mainboard/google/sarien/variants/arcada/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32361/1
diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index b66e1dd..7583b51 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -32,9 +32,9 @@ /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ /* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 1, DEEP), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_ACC1_INT# */
Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32361 )
Change subject: mb/google/sarien: Configure both GPP_H12 and GPP_H13 for SSD on Arcada ......................................................................
Patch Set 2: Code-Review+1
This change is ready for review.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32361 )
Change subject: mb/google/sarien: Configure both GPP_H12 and GPP_H13 for SSD on Arcada ......................................................................
Patch Set 2: Code-Review+2
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32361 )
Change subject: mb/google/sarien: Configure both GPP_H12 and GPP_H13 for SSD on Arcada ......................................................................
mb/google/sarien: Configure both GPP_H12 and GPP_H13 for SSD on Arcada
Currently, Arcada only supports D3hot during S0iX and there is leakage power around 5~10mW depending on SSD vendors. To support D3cold for SSD during S0iX, one MOSFET will be added on DVT2 and two GPIOs are required to be configured. GPP_H13 is to control SSD_SCP_PWR_EN(power enable) and GPP_H12 is to control SSD reset.
BUG=b:130741066 TEST=Measure SSD power during S0iX from Arcada(DVT2)
Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50 Signed-off-by: Roy Mingi Park roy.mingi.park@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32361 Reviewed-by: Duncan Laurie dlaurie@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/sarien/variants/arcada/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Roy Mingi Park: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index b66e1dd..2a0ead8 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -211,8 +211,8 @@ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ -/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), -/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),
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Duncan Laurie (Code Review) -
Roy Mingi Park (Code Review)