Change in coreboot[master]: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43412 )

Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
......................................................................

mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4

Two usb Type-C ports under the actual mux device. Each port has its own
ACPI device entry. These nodes are the ones that the USB Type-C
port/connector device will refer to in order to configure the mux.

TEST=Built image-tglrvp-up4.bin successfully.

Signed-off-by: John Zhao 
Change-Id: I8423ddbb5bc189899a9e19e7da6e2ee7b7fecc18
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
1 file changed, 22 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/43412/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index b08cd3c..097ae68 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -254,7 +254,28 @@
    	device pci 1e.3 off end # GSPI1			0xA0AB
    	device pci 1f.0 on  end # eSPI			0xA080 - A09F
    	device pci 1f.1 on  end # P2SB			0xA0A0
-		device pci 1f.2 hidden end # PMC		0xA0A1
+		device pci 1f.2 hidden  # PMC                   0xA0A1
+			# The pmc_mux chip driver is a placeholder for the
+			# PMC.MUX device in the ACPI hierarchy.
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "6"
+						register "usb3_port_number" = "3"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "5"
+						register "usb3_port_number" = "2"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 1 on end
+					end
+				end
+			end
+		end # PMC
    	device pci 1f.3 on  end # Intel HD audio	0xA0C8-A0CF
    	device pci 1f.4 on  end # SMBus			0xA0A3
    	device pci 1f.5 on  end # SPI			0xA0A4

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43412 )

Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
......................................................................

Patch Set 1: Code-Review+1

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43412 )

Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43412/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43412/1//COMMIT_MSG@13 
PS1, Line 13: TEST=Built image-tglrvp-up4.bin successfully.
Can you add more detail test info?

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43412 )

Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43412/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43412/1//COMMIT_MSG@13 
PS1, Line 13: TEST=Built image-tglrvp-up4.bin successfully.
> Can you add more detail test info?

I don't have RVP Y board for testing. The usb2/usb3 port numbers are from EC tglrvpy_ite board configuration.

[Caveh Jalali (Code Review)]

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43412 )

Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43412/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43412/1//COMMIT_MSG@13 
PS1, Line 13: TEST=Built image-tglrvp-up4.bin successfully.
> I don't have RVP Y board for testing. […]

have you cross referenced the USB port numbers with the schematics for your -Y board? the orientation is probably correct if your
retimer "corrects" the SBU orientation (e.g. burnside bridge).

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43412 )

Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43412/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43412/1//COMMIT_MSG@13 
PS1, Line 13: TEST=Built image-tglrvp-up4.bin successfully.
> have you cross referenced the USB port numbers with the schematics for your -Y board? the orientatio […]

USB port numbers had been crossed reference from the TGLRVP Y schematic. USB2 and USB3 port numbers are referred from Y boards's EC USB-C ports configuration. There are retimers for all ports.

[Caveh Jalali (Code Review)]

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43412 )

Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
......................................................................

Patch Set 1: Code-Review+2

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43412 )

Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43412 )

Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
......................................................................

mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4

Two usb Type-C ports under the actual mux device. Each port has its own
ACPI device entry. These nodes are the ones that the USB Type-C
port/connector device will refer to in order to configure the mux.

TEST=Built image-tglrvp-up4.bin successfully.

Signed-off-by: John Zhao 
Change-Id: I8423ddbb5bc189899a9e19e7da6e2ee7b7fecc18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43412
Tested-by: build bot (Jenkins) 
Reviewed-by: Wonkyu Kim 
Reviewed-by: Caveh Jalali 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
1 file changed, 22 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Caveh Jalali: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index b08cd3c..097ae68 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -254,7 +254,28 @@
    	device pci 1e.3 off end # GSPI1			0xA0AB
    	device pci 1f.0 on  end # eSPI			0xA080 - A09F
    	device pci 1f.1 on  end # P2SB			0xA0A0
-		device pci 1f.2 hidden end # PMC		0xA0A1
+		device pci 1f.2 hidden  # PMC                   0xA0A1
+			# The pmc_mux chip driver is a placeholder for the
+			# PMC.MUX device in the ACPI hierarchy.
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "6"
+						register "usb3_port_number" = "3"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "5"
+						register "usb3_port_number" = "2"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 1 on end
+					end
+				end
+			end
+		end # PMC
    	device pci 1f.3 on  end # Intel HD audio	0xA0C8-A0CF
    	device pci 1f.4 on  end # SMBus			0xA0A3
    	device pci 1f.5 on  end # SPI			0xA0A4