Change in coreboot[master]: soc/mediatek/mt8195: Enable mt8195 auxadc

[Rex-BC Chen (Code Review)]

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55155 )

Change subject: soc/mediatek/mt8195: Enable mt8195 auxadc
......................................................................

soc/mediatek/mt8195: Enable mt8195 auxadc

Enable auxadc on MediaTek mt8195 platform.

Signed-off-by: Zhiqiang Ma 
Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49
---
M src/soc/mediatek/mt8195/Makefile.inc
M src/soc/mediatek/mt8195/include/soc/addressmap.h
A src/soc/mediatek/mt8195/include/soc/auxadc.h
A src/soc/mediatek/mt8195/include/soc/efuse.h
4 files changed, 45 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/55155/1

diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
old mode 100644
new mode 100755
index 3bdb47c..e053638
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -1,5 +1,6 @@
 ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)

+bootblock-y += ../common/auxadc.c
 bootblock-y += bootblock.c
 bootblock-y += ../common/eint_event.c
 bootblock-y += ../common/flash_controller.c
@@ -12,6 +13,7 @@
 bootblock-y += ../common/uart.c
 bootblock-y += ../common/wdt.c

+verstage-y += ../common/auxadc.c
 verstage-y += ../common/flash_controller.c
 verstage-y += ../common/gpio.c gpio.c
 verstage-y += ../common/i2c.c i2c.c
@@ -20,6 +22,7 @@
 verstage-y += ../common/uart.c
 verstage-y += ../common/wdt.c

+romstage-y += ../common/auxadc.c
 romstage-y += ../common/cbmem.c
 romstage-y += ../common/clkbuf.c
 romstage-y += ../common/dram_init.c
@@ -44,6 +47,7 @@
 romstage-y += ../common/mt6359p.c mt6359p.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c

+ramstage-y += ../common/auxadc.c
 ramstage-y += emi.c
 ramstage-y += ../common/flash_controller.c
 ramstage-y += ../common/gpio.c gpio.c
diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h
old mode 100644
new mode 100755
index e5195ca..5d5c937
--- a/src/soc/mediatek/mt8195/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h
@@ -50,7 +50,7 @@
    DPM_PM_SRAM_BASE2	= IO_PHYS + 0x00A00000,
    DPM_DM_SRAM_BASE2	= IO_PHYS + 0x00A20000,
    DPM_CFG_BASE2		= IO_PHYS + 0x00A40000,
-	AUXADC_BASE		= IO_PHYS + 0x01001000,
+	AUXADC_BASE		= IO_PHYS + 0x01002000,
    UART0_BASE		= IO_PHYS + 0x01001100,
    PERICFG_AO_BASE		= IO_PHYS + 0x01003000,
    SPI0_BASE		= IO_PHYS + 0x0100A000,
diff --git a/src/soc/mediatek/mt8195/include/soc/auxadc.h b/src/soc/mediatek/mt8195/include/soc/auxadc.h
new file mode 100755
index 0000000..f697831
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/auxadc.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MTK_ADC_H
+#define _MTK_ADC_H
+
+#include <soc/auxadc_common.h>
+#include <soc/infracfg.h>
+#include <stdint.h>
+
+typedef struct mtk_auxadc_regs {
+	uint32_t con0;
+	uint32_t con1;
+	uint32_t con1_set;
+	uint32_t con1_clr;
+	uint32_t con2;
+	uint32_t data[16];
+	uint32_t reserved[16];
+	uint32_t misc;
+} mtk_auxadc_regs;
+
+static struct mt8195_infracfg_ao_regs *const mtk_infracfg = mt8195_infracfg_ao;
+
+#endif
diff --git a/src/soc/mediatek/mt8195/include/soc/efuse.h b/src/soc/mediatek/mt8195/include/soc/efuse.h
new file mode 100755
index 0000000..b746170
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/efuse.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MTK_EFUSE_H
+#define _MTK_EFUSE_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct efuse_regs {
+	uint32_t rserved[130];
+	uint32_t adc_cali_reg;
+};
+
+check_member(efuse_regs, adc_cali_reg, 0x208);
+static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE;
+
+#endif