Change in ...coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...

[junaid (Code Review)]

junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798

Change subject: for review d945gclf/Kconig  and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG
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for review d945gclf/Kconig  and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG

Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5
Signed-off-by: junaid 
---
M src/mainboard/intel/d945gclf/Kconfig
M src/mainboard/intel/d945gclf/devicetree.cb
2 files changed, 37 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1

diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
index 70fa848..906dd01 100644
--- a/src/mainboard/intel/d945gclf/Kconfig
+++ b/src/mainboard/intel/d945gclf/Kconfig
@@ -20,7 +20,8 @@
    select NORTHBRIDGE_INTEL_I945
    select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
    select SOUTHBRIDGE_INTEL_I82801GX
-	select SUPERIO_SMSC_LPC47M15X
+## changed as per Advantech SOM 4461
+	select SUPERIO_WINBOND_W83627DHG
    select HAVE_OPTION_TABLE
    select HAVE_CMOS_DEFAULT
    select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index 90c517f..864775a 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -65,44 +65,42 @@
    		device pci 1d.1 on end # USB UHCI
    		device pci 1d.2 on end # USB UHCI
    		device pci 1d.3 off end # USB UHCI
-			device pci 1d.7 on end # USB2 EHCI
-			device pci 1e.0 on end # PCI bridge
-			device pci 1e.2 off end # AC'97 Audio
+			device pci 1d.7 on end	# USB2 EHCI
+			device pci 1e.0 on end	# PCI bridge
+			device pci 1e.2 off end	# AC'97 Audio
    		device pci 1e.3 off end # AC'97 Modem
                         device pci 1f.0 on # LPC bridge
-                                chip superio/smsc/lpc47m15x
-					device pnp 2e.0 off		# Floppy
-					end
-					device pnp 2e.3 off		# Parport
-					end
-                                        device pnp 2e.4 on
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 2e.5 on
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-						irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
-                                        end
-					device pnp 2e.7 on		# Keyboard+Mouse
-						 io 0x60 = 0x60
-						 io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-						irq 0xf0 = 0x82		# HW accel A20.
-					end
-					device pnp 2e.8 on		# GAME
-						# all default
-					end
-					device pnp 2e.a on		# PME
-					end
-					device pnp 2e.b on		# MPU
-					end
-                                end
-                        end
+					chip superio/winbond/w83627dhg
+						device pnp 2e.0 off end	# Floppy
+						device pnp 2e.1 off end	# Parallel Port
+						device pnp 2e.2 on	# COM1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.3 on		# COM2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.5 on		# Keyboard,Mouse
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+							irq 0x72 = 12
+						end
+						#device pnp 2e.6 off	end	# SPI
+						device pnp 2e.307 off	end	# GPIO6
+						device pnp 2e.8 off	end	# WDTO, PLED
+						device pnp 2e.009 off	end	# GPIO2
+						device pnp 2e.109 off	end	# GPIO3
+						device pnp 2e.209 off	end	# GPIO4
+						device pnp 2e.309 off	end	# GPIO5
+						device pnp 2e.A off	end	# ACPI
+						device pnp 2e.B off	end	# HW Monitor
+					end # w83627dhg
+			end
    		device pci 1f.1 off end # IDE
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
-                end
-        end
+			device pci 1f.2 on end  # SATA
+			device pci 1f.3 on end  # SMBus
+		end
+	end
 end

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30798 )

Change subject: for review d945gclf/Kconig  and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG
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Patch Set 1:

Deprecated in favor of CB:30977, please abandon this change.

Change in coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/30798 )

Change subject: for review d945gclf/Kconig  and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG
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Removed Code-Review-2 by Kyösti Mälkki

[M] Change in coreboot[master]: for review d945gclf/Kconig and devicetree.cb . these files are modif...

[Stefan Reinauer (Code Review)]

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30798?usp=email )

Change subject: for review d945gclf/Kconig  and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG
......................................................................

Abandoned