[S] Change in coreboot[main]: soc/intel/cmn/pmc: Perform PM register init for CSE

[Subrata Banik (Code Review)]

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik.

Hello Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85025?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/cmn/pmc: Perform PM register init for CSE
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soc/intel/cmn/pmc: Perform PM register init for CSE

Before entering FSP-M, AP firmware must ensure the PM1_CNT register
reflects the correct sleep state if a global reset occurred.

This is crucial when Intel CSE has reset the system, as indicated by
the global reset bit and wake status register.

If PM1_CNT doesn't contain a valid sleep state after a CSE reset, AP
firmware must enforce an S5 exit path before handing control to FSP-M
for CSE initialization. This ensures proper system initialization and
avoids potential issues caused by an inconsistent sleep state.

Additionally, clears the PM1 status register (PM1_STS) after retrieving
the power state. This prevents stale status information from persisting
across power cycles, which could lead to confusion during subsequent
boots.

BUG=b:265939425
TEST=Verified that `prev_sleep_state` holds the correct value
(5 for S5) after CSE performs a global reset.

Fixes: Inconsistent sleep state after CSE reset.

Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/pmc/pmclib.c
1 file changed, 46 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/85025/3