[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware

[Arthur Heymans (Code Review)]

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70265 )

Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware
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Patch Set 8:

(1 comment)

File src/soc/intel/xeon_sp/acpi.c:

https://review.coreboot.org/c/coreboot/+/70265/comment/c2d2fb64_0c7d4d6a 
PS6, Line 100: 	xeonsp_ioapic_bases[index++] = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase;
> What I found odd was creating two xeons_ioapic_bases[] entries from one HOB entry.

So Stack == 0, Socket == 0 has both the PCH IOAPIC which is what it returns. The IIO stack ioapic is at 0x1000 above that one.

I should add that comment back:
/*
 * Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
 * The IIO IOAPIC is placed at 0x1000 from the reported base.
 */