Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46920 )
Change subject: cpu/intel/haswell: Allow tuning VR for C-state operations ......................................................................
cpu/intel/haswell: Allow tuning VR for C-state operations
Apply commit ff0f460 (broadwell: Add configuration for tuning VR for C-state operations) to Haswell, in preparation for unification.
Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 50 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46920/1
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 9db1ad3..16f1079 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -3,6 +3,35 @@ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC
+#include <stdbool.h> +#include <stdint.h> + +struct cpu_vr_config { + /* + * Minimum voltage for C6/C7 state: + * 0x67 = 1.6V (full swing) + * ... + * 0x79 = 1.7V + * ... + * 0x83 = 1.8V (no swing) + */ + uint8_t cpu_min_vid; + + /* + * Set slow VR ramp rate on C-state exit: + * 0 = Fast VR ramp rate / 2 + * 1 = Fast VR ramp rate / 4 + * 2 = Fast VR ramp rate / 8 + * 3 = Fast VR ramp rate / 16 + */ + uint8_t slow_ramp_rate_set; + + /* Enable slow VR ramp rate */ + bool slow_ramp_rate_enable; +}; + struct cpu_intel_haswell_config { int tcc_offset; /* TCC Activation Offset */ + + struct cpu_vr_config vr_config; }; diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5e9b742..5838f1f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -249,8 +249,17 @@
static void initialize_vr_config(void) { + struct cpu_vr_config vr_config = { 0 }; msr_t msr;
+ const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (lapic && lapic->chip_info) { + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + vr_config = conf->vr_config; + } + printk(BIOS_DEBUG, "Initializing VR config.\n");
/* Configure VR_CURRENT_CONFIG. */ @@ -280,13 +289,23 @@ msr.hi &= ~(1 << (51 - 32)); /* Enable decay mode on C-state entry. */ msr.hi |= (1 << (52 - 32)); + /* Set the slow ramp rate */ if (haswell_is_ult()) { - /* Set the slow ramp rate to be fast ramp rate / 4 */ msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); + /* Configure the C-state exit ramp rate. */ + if (vr_config.slow_ramp_rate_enable) { + /* Configured slow ramp rate. */ + msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); + /* Set exit ramp rate to slow. */ + msr.hi &= ~(1 << (50 - 32)); + } else { + /* Fast ramp rate / 4. */ + msr.hi |= (1 << (53 - 32)); + } } /* Set MIN_VID (31:24) to allow CPU to have full control. */ msr.lo &= ~0xff000000; + msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; wrmsr(MSR_VR_MISC_CONFIG, msr);
/* Configure VR_MISC_CONFIG2 MSR. */
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46920
to look at the new patch set (#6).
Change subject: cpu/intel/haswell: Allow tuning VR for C-state operations ......................................................................
cpu/intel/haswell: Allow tuning VR for C-state operations
Apply commit ff0f460 (broadwell: Add configuration for tuning VR for C-state operations) to Haswell, in preparation for unification.
Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 50 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46920/6
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46920
to look at the new patch set (#12).
Change subject: cpu/intel/haswell: Allow tuning VR for C-state operations ......................................................................
cpu/intel/haswell: Allow tuning VR for C-state operations
Apply commit ff0f460e76 (broadwell: Add configuration for tuning VR for C-state operations) to Haswell, in preparation for unification.
Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 50 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46920/12
Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46920 )
Change subject: cpu/intel/haswell: Allow tuning VR for C-state operations ......................................................................
Patch Set 14: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46920 )
Change subject: cpu/intel/haswell: Allow tuning VR for C-state operations ......................................................................
cpu/intel/haswell: Allow tuning VR for C-state operations
Apply commit ff0f460e76 (broadwell: Add configuration for tuning VR for C-state operations) to Haswell, in preparation for unification.
Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46920 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 50 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 6afed37..7c2df10 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -3,6 +3,33 @@ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC
+#include <stdbool.h> +#include <stdint.h> + +struct cpu_vr_config { + /* + * Minimum voltage for C6/C7 state: + * 0x67 = 1.6V (full swing) + * ... + * 0x79 = 1.7V + * ... + * 0x83 = 1.8V (no swing) + */ + uint8_t cpu_min_vid; + + /* + * Set slow VR ramp rate on C-state exit: + * 0 = Fast VR ramp rate / 2 + * 1 = Fast VR ramp rate / 4 + * 2 = Fast VR ramp rate / 8 + * 3 = Fast VR ramp rate / 16 + */ + uint8_t slow_ramp_rate_set; + + /* Enable slow VR ramp rate */ + bool slow_ramp_rate_enable; +}; + struct cpu_intel_haswell_config { int c1_battery; /* ACPI C1 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */ @@ -13,4 +40,6 @@ int c3_acpower; /* ACPI C3 on AC Power */
int tcc_offset; /* TCC Activation Offset */ + + struct cpu_vr_config vr_config; }; diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 369ace9..dd1970c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -249,8 +249,17 @@
static void initialize_vr_config(void) { + struct cpu_vr_config vr_config = { 0 }; msr_t msr;
+ const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (lapic && lapic->chip_info) { + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + vr_config = conf->vr_config; + } + printk(BIOS_DEBUG, "Initializing VR config.\n");
/* Configure VR_CURRENT_CONFIG. */ @@ -280,13 +289,23 @@ msr.hi &= ~(1 << (51 - 32)); /* Enable decay mode on C-state entry. */ msr.hi |= (1 << (52 - 32)); + /* Set the slow ramp rate */ if (haswell_is_ult()) { - /* Set the slow ramp rate to be fast ramp rate / 4 */ msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); + /* Configure the C-state exit ramp rate. */ + if (vr_config.slow_ramp_rate_enable) { + /* Configured slow ramp rate. */ + msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); + /* Set exit ramp rate to slow. */ + msr.hi &= ~(1 << (50 - 32)); + } else { + /* Fast ramp rate / 4. */ + msr.hi |= (1 << (53 - 32)); + } } /* Set MIN_VID (31:24) to allow CPU to have full control. */ msr.lo &= ~0xff000000; + msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; wrmsr(MSR_VR_MISC_CONFIG, msr);
/* Configure VR_MISC_CONFIG2 MSR. */
-
Angel Pons (Code Review) -
Nico Huber (Code Review)