Change in coreboot[master]: mb/google/asurada: change EC SPI to 3M

[Yidi Lin (Code Review)]

Hello Hung-Te Lin,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/46394

to review the following change.

Change subject: mb/google/asurada: change EC SPI to 3M
......................................................................

mb/google/asurada: change EC SPI to 3M

To prevent timeout on long EC packet, we should increase EC SPI speed to
the same value that kernel is using (3M).

BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot

Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
---
M src/mainboard/google/asurada/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46394/1

diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c
index 04e8898..647555a 100644
--- a/src/mainboard/google/asurada/bootblock.c
+++ b/src/mainboard/google/asurada/bootblock.c
@@ -7,7 +7,7 @@

void bootblock_mainboard_init(void)
 {
-	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
+	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
    mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
    setup_chromeos_gpios();
    gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING);

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: change EC SPI to 3M
......................................................................

Patch Set 1: Code-Review+2

Can we move this to the starting of this chain, to get it verified and merged?

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: change EC SPI to 3M
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46394/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46394/4//COMMIT_MSG@9 
PS4, Line 9: To prevent timeout on long EC packet,
Where does it time out?

https://review.coreboot.org/c/coreboot/+/46394/4//COMMIT_MSG@16 
PS4, Line 16: 
Missing Signed-off-by line.

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: change EC SPI to 3M
......................................................................

Patch Set 6:

No Signed-off-by line in commit message

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: change EC SPI to 3M
......................................................................

Patch Set 6: -Code-Review

No Signed-off-by line in commit message

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#7) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: change EC SPI to 3M
......................................................................

mb/google/asurada: change EC SPI to 3M

To prevent timeout on long EC packet, we should increase EC SPI speed to
the same value that kernel is using (3M).

BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot

Signed-off-by: Hung-Te Lin 
Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
---
M src/mainboard/google/asurada/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46394/7

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46394

to look at the new patch set (#8).

Change subject: mb/google/asurada: change EC SPI to 3M
......................................................................

mb/google/asurada: change EC SPI to 3M

To prevent timeout on long EC packet, we should increase EC SPI speed to
the same value that kernel is using (3M).

BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot

Signed-off-by: Hung-Te Lin 
Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
---
M src/mainboard/google/asurada/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46394/8

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: change EC SPI to 3M
......................................................................

Patch Set 8:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46394/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46394/4//COMMIT_MSG@9 
PS4, Line 9: To prevent timeout on long EC packet,
> Where does it time out?

@yidi, please try this:

mb/google/asurada: fix timeout on EC commands

The Asurada EC is using large packet (256B) mode, and we were
 seeing lots of time out error on various commands.

The AcceptTimeoutUs in EC SPI driver is hard-coded at 5000,
 and that is too small for large packet running in 1M so we
 should change EC SPI to the same value that kernel is using (3M).

https://review.coreboot.org/c/coreboot/+/46394/4//COMMIT_MSG@16 
PS4, Line 16:
> Missing Signed-off-by line.

Done

Change in coreboot[master]: mb/google/asurada: fix EC commands timeout

[Hung-Te Lin (Code Review)]

Hung-Te Lin has uploaded a new patch set (#9) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: fix EC commands timeout
......................................................................

mb/google/asurada: fix EC commands timeout

The Asurada EC is using the large packet (256B) mode, and we were
seeing lots of timeout errors on various commands.

The AcceptTimeoutUs in EC SPI driver is hard-coded at 5000,
and that is too small for large packet running in 1M so we
should change EC SPI to the same value that kernel is using (3M).

BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot

Signed-off-by: Hung-Te Lin 
Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
---
M src/mainboard/google/asurada/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46394/9

Change in coreboot[master]: mb/google/asurada: fix EC commands timeout

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: fix EC commands timeout
......................................................................

Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46394/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46394/4//COMMIT_MSG@9 
PS4, Line 9: To prevent timeout on long EC packet,
> @yidi, please try this: […]

Done

Change in coreboot[master]: mb/google/asurada: fix EC commands timeout

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: fix EC commands timeout
......................................................................

Patch Set 9: Code-Review+2

Change in coreboot[master]: mb/google/asurada: fix EC commands timeout

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46394 )

Change subject: mb/google/asurada: fix EC commands timeout
......................................................................

mb/google/asurada: fix EC commands timeout

The Asurada EC is using the large packet (256B) mode, and we were
seeing lots of timeout errors on various commands.

The AcceptTimeoutUs in EC SPI driver is hard-coded at 5000,
and that is too small for large packet running in 1M so we
should change EC SPI to the same value that kernel is using (3M).

BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot

Signed-off-by: Hung-Te Lin 
Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46394
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/asurada/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c
index 04e8898..647555a 100644
--- a/src/mainboard/google/asurada/bootblock.c
+++ b/src/mainboard/google/asurada/bootblock.c
@@ -7,7 +7,7 @@

void bootblock_mainboard_init(void)
 {
-	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
+	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
    mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
    setup_chromeos_gpios();
    gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING);