[S] Change in coreboot[master]: [Only for test]i945/acpi/hostbridge.asl: include "i945.h"

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68219 )

Change subject: [Only for test]i945/acpi/hostbridge.asl: include "i945.h"
......................................................................

[Only for test]i945/acpi/hostbridge.asl: include "i945.h"

Signed-off-by: Elyes Haouas 
Change-Id: I2abbacea44c456a80267e407ce47bd22787a72a9
---
M src/northbridge/intel/i945/acpi/hostbridge.asl
M src/northbridge/intel/i945/i945.h
2 files changed, 23 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/68219/1

diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl
index 6eba415..199cc05 100644
--- a/src/northbridge/intel/i945/acpi/hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/hostbridge.asl
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/ioapic.h>
+#include <northbridge/intel/i945/i945.h>

Name(_HID,EISAID("PNP0A08"))	// PCIe
 Name(_CID,EISAID("PNP0A03"))	// PCI
@@ -14,30 +15,30 @@
    OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
    Field (MCHP, DWordAcc, NoLock, Preserve)
    {
-		Offset (0x40),	/* EPBAR */
+		Offset (EPBAR),
    	EPEN,	 1,	/* Enable */
    	,	11,
    	EPBR,	20,	/* EPBAR */

-		/* MCHBAR */
+		Offset (MCHBAR),
    	MHEN,	 1,	/* Enable */
    	,	13,
    	MHBR,	18,	/* MCHBAR */

-		/* PCIe BAR */
+		Offset (PCIEXBAR),
    	PXEN,	 1,	/* Enable */
    	PXSZ,	 2,	/* BAR size */
    	,	23,
    	PXBR,	 6,	/* PCIec BAR */

-		/* DMIBAR */
+		Offset (DMIBAR),
    	DMEN,	 1,	/* Enable */
    	,	11,
    	DMBR,	20,	/* DMIBAR */

/* ... */

-		Offset (0x90),	/* PAM0 */
+		Offset (PAM0),
    	,	 4,
    	PM0H,	 2,
    	,	 2,
@@ -72,11 +73,11 @@
    	PM6H,	 2,
    	,	 2,

-		Offset (0x9c),	/* Top of Low Used Memory */
+		Offset (TOLUD),
    	,	 3,
    	TLUD,	 5,

-		Offset (0xa0),	/* Top of Used Memory */
+		Offset (TOM),
    	TOM,	16,
    }
 }
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 4818a73..ac290c8 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -3,8 +3,10 @@
 #ifndef NORTHBRIDGE_INTEL_I945_H
 #define NORTHBRIDGE_INTEL_I945_H

+#ifndef __ACPI__
 #include <northbridge/intel/common/fixed_bars.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
+#endif

#define DEFAULT_X60BAR		0xfed13000

@@ -321,6 +323,7 @@

#define DMIDRCCFG	0xeb4	/* 32bit */

+#ifndef __ACPI__
 int i945_silicon_revision(void);
 void i945_early_initialization(void);
 void i945_late_initialization(int s3resume);
@@ -345,4 +348,6 @@
 /* Optional: mainboard callback to get SPD map */
 void mainboard_get_spd_map(u8 spd_map[4]);

+#endif /* __ACPI__ */
+
 #endif /* NORTHBRIDGE_INTEL_I945_H */