[S] Change in coreboot[master]: soc/intel/cometlake: Enable early caching of RAMTOP region

[Matt DeVillier (Code Review)]

Attention is currently required from: Sean Rhodes, Subrata Banik.

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74517 )

Change subject: soc/intel/cometlake: Enable early caching of RAMTOP region
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Patch Set 4:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/74517/comment/c4ce3649_42c2895b 
PS4, Line 12: Purpose of this feature is to cache the TOM (with a fixed size of
            : 16MB)
how does this affect CML boards with a 32MB flash? There's a handful of google/hatch and puff variants which use 32MB flash