Change in coreboot[master]: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48325 )

Change subject: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
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soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration

coreboot already unconditionally enables CLKRUN_EN in SoC common code.

Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.

Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by:  Felix Singer 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/kontron/bsl6/devicetree.cb
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
4 files changed, 0 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
   Felix Singer: Looks good to me, but someone else must approve

diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 43f272e..b51c73c 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -56,8 +56,6 @@

register "serirq_mode" = "SERIRQ_CONTINUOUS"

-	register "PmConfigPciClockRun" = "1"
-
    # Enable Root Ports 3, 4 and 9
    register "PcieRpEnable[2]" = "1" # Ethernet controller
    register "PcieRpClkReqSupport[2]" = "1"
diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb
index 6bdfcaf..8ad7852 100644
--- a/src/mainboard/kontron/bsl6/devicetree.cb
+++ b/src/mainboard/kontron/bsl6/devicetree.cb
@@ -10,7 +10,6 @@
    register "PmConfigSlpS4MinAssert"	= "SLP_S4_MIN_ASSERT_4S"
    register "PmConfigSlpSusMinAssert"	= "SLP_SUS_MIN_ASSERT_4S"
    register "PmConfigSlpAMinAssert"	= "SLP_A_MIN_ASSERT_2S"
-	register "PmConfigPciClockRun"		= "1"
    register "PmConfigPwrCycDur"		= "RESET_POWER_CYCLE_4S"

# VR Settings Configuration for 2 Domains
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index c9519cd..ef16f38 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -338,7 +338,6 @@
    params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
    params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert;
    params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert;
-	params->PchPmLpcClockRun = config->PmConfigPciClockRun;
    params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp;
    params->PchPmPwrBtnOverridePeriod =
    			config->PmConfigPwrBtnOverridePeriod;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index f4744c9..7d9d934 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -377,11 +377,6 @@
    } PmConfigSlpAMinAssert;

/*
-	 * This member describes whether or not the PCI ClockRun feature of PCH
-	 * should be enabled. Values 0: Disabled, 1: Enabled
-	 */
-	u8 PmConfigPciClockRun;
-	/*
     * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled,
     * 1: Enabled
     */