Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40020 )
Change subject: sb/intel/bd82x6x: Tidy up code and comments ......................................................................
sb/intel/bd82x6x: Tidy up code and comments
- Reformat and reflow many lines of code - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Add some macros to factor out clutter
With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.
Change-Id: Ie38c4ed7c2956bf96cffd84276ab48d4b9eab5db Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_rcba.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/early_thermal.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c 25 files changed, 491 insertions(+), 560 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/40020/1
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 316fafc..d904d33 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -31,9 +31,7 @@ reg32 |= val; write32(port, reg32);
- /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -95,8 +93,8 @@ }
/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */
static int wait_for_ready(u8 *base) @@ -116,9 +114,8 @@ }
/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the codec is non-operative. */
static int wait_for_valid(u8 *base) @@ -135,8 +132,7 @@ int timeout = 1000; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index ef2ee0e..e8d8520 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -22,7 +22,7 @@ static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ - RCBA32(GCS) &= (~0x04); + RCBA32(GCS) &= ~(1 << 2); }
static void set_spi_speed(void) diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 94715de..a83d1b3 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -88,4 +88,4 @@ struct intel_swseq_spi_config spi; };
-#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 184f72a..91856a5 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -137,7 +137,7 @@
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); - printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1); + printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", (me_fws2 & 0x1)); printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1); printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3); printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4); @@ -208,7 +208,7 @@
me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); - printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1); + printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", (me_fws2 & 0x1)); printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1); printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3); printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 530f11a..05f93db 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -19,15 +19,13 @@
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
-static void -wait_iobp(void) +static void wait_iobp(void) { while (RCBA8(IOBPS) & 1) ; // implement timeout? }
-static u32 -read_iobp(u32 address) +static u32 read_iobp(u32 address) { u32 ret;
@@ -40,12 +38,13 @@ return ret; }
-static void -write_iobp(u32 address, u32 val) +static void write_iobp(u32 address, u32 val) { - /* this function was probably pch_iobp_update with the andvalue - * being 0. So either the IOBP read can be removed or this function - * and the pch_iobp_update function in ramstage could be merged */ + /* + * This function was probably pch_iobp_update with the andvalue being 0. + * So, either the IOBP read can be removed or this function and the + * pch_iobp_update function in ramstage could be merged + */ read_iobp(address); RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; wait_iobp(); @@ -88,15 +87,17 @@ * serialice traces. */
- /* Virtual Channel 0 Resource Control Register. + /* + * Virtual Channel 0 Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC0 and TC3 and TC4 to VC0. */ - RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + /* FIXME: Read back? */
- /* Virtual Channel 1 Resource Control Register. + /* + * Virtual Channel 1 Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC1 and TC5 to VC1. @@ -105,7 +106,8 @@ /* Read back register */ RCBA32(V1CTL);
- /* Virtual Channel private Resource Control Register. + /* + * Virtual Channel private Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC2 and TC6 to VCp. @@ -114,12 +116,14 @@ /* Read back register */ RCBA32(CIR31);
- /* Virtual Channel ME Resource Control Register. + /* + * Virtual Channel ME Resource Control Register. * Enable channel. * Set Virtual Channel Identifier. * Map TC7 to VCm. */ RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1); + /* FIXME: Read back? */
/* Lock Virtual Channel Resource control register. */ RCBA32(CIR0) |= TCLOCKDN; @@ -137,11 +141,9 @@ ; }
-void -early_pch_init_native (void) +void early_pch_init_native (void) { - pci_write_config8 (SOUTHBRIDGE, 0xa6, - pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); + pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2);
RCBA32(CIR1) = 0x00109000; RCBA32(REC); // !!! = 0x00000000 @@ -278,9 +280,9 @@ * - 0x3f8-0x3ff COMA */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF1_LPC_EN | COMA_LPC_EN | LPT_LPC_EN | KBC_LPC_EN | + CNF2_LPC_EN | COMB_LPC_EN | FDD_LPC_EN | MC_LPC_EN);
const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_bd82x6x_config *config = NULL; diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 915a935..9785e2c 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -5,21 +5,18 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include "pch.h"
-void -southbridge_configure_default_intmap(void) +void southbridge_configure_default_intmap(void) { /* - * For the PCH internal PCI functions, provide a reasonable - * default IRQ mapping that utilizes only PIRQ A to D. Higher - * PIRQs are sometimes used for other on-board chips that - * require an edge triggered interrupt which is not shareable. + * For the PCH internal PCI functions, provide a reasonable default IRQ mapping that + * utilizes only PIRQ A to D. Higher PIRQs are sometimes used for other on-board chips + * that require an edge triggered interrupt which is not shareable. */
/* - * We use a linear mapping for the pin numbers. They are not - * physical pins, and thus, have no relation between the dif- - * ferent devices. Only rule we must obey is that a single- - * function device has to use pin A. + * We use a linear mapping for the pin numbers. They are not physical pins, and thus, + * have no relation between the different devices. Only rule we must obey is that a + * single-function device has to use pin A. */ RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); @@ -35,19 +32,18 @@ RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
/* - * For the PIRQ allocation the following was taken into - * account: - * o Interrupts of the PCIe root ports are only about - * events at the ports, not downstream devices. So we - * don't expect many interrupts there and ignore them. - * o We don't expect to talk constantly to the ME either - * so ignore that, too. Same for SMBus and the thermal - * device. - * o Second SATA interface is only used in non-AHCI mode - * so unlikely to coexist with modern interfaces (e.g. - * xHCI). - * o An OS that knows USB3 will likely also know how to - * use MSI. + * For the PIRQ allocation the following was taken into account: + * + * o Interrupts of the PCIe root ports are only about events at the ports, not + * downstream devices. So we don't expect many interrupts there and ignore them. + * + * o We don't expect to talk constantly to the ME either so ignore that, too. Same + * for SMBus and the thermal device. + * + * o Second SATA interface is only used in non-AHCI mode so unlikely to coexist with + * modern interfaces (e.g. xHCI). + * + * o An OS that knows USB3 will likely also know how to use MSI. * * The functions that might matter first: * @@ -83,8 +79,7 @@ (void) RCBA16(OIC); }
-void -southbridge_rcba_config(void) +void southbridge_rcba_config(void) { RCBA32(FD) = PCH_DISABLE_ALWAYS; } diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index f3151af..c19a9d9 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
-#include <device/pci_ops.h> #include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <device/smbus_host.h> #include "pch.h"
@@ -14,15 +15,14 @@ int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 3);
/* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1;
/* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); + pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 8de31e6..ebf3e80 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -1,69 +1,68 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
-#include <device/mmio.h> -#include <device/pci_ops.h> -#include "pch.h" -#include "cpu/intel/model_206ax/model_206ax.h" #include <cpu/x86/msr.h> +#include <device/mmio.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include "cpu/intel/model_206ax/model_206ax.h" +#include "pch.h"
-static void write8p(uintptr_t addr, uint32_t val) +static void write8p(uintptr_t addr, const uint32_t val) { write8((u8 *)addr, val); }
-static void write16p(uintptr_t addr, uint32_t val) +static void write16p(uintptr_t addr, const uint32_t val) { write16((u16 *)addr, val); }
-static uint16_t read16p (uintptr_t addr) +static uint16_t read16p(const uintptr_t addr) { return read16((u16 *)addr); }
-/* Early thermal init, must be done prior to giving ME its memory - which is done at the end of raminit. */ +/* We use this temporary BAR to program some registers in the Thermal device's MMIO window */ +#define THERMAL_BASE (0x40000000) + +/* Early thermal init, must be done before giving ME its memory, which is done after raminit */ void early_thermal_init(void) { - pci_devfn_t dev; + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 6); msr_t msr;
- dev = PCI_DEV(0x0, 0x1f, 0x6); + /* Program address for temporary BAR */ + pci_write_config32(dev, 0x40, THERMAL_BASE); /* TBARB */ + pci_write_config32(dev, 0x44, 0); /* TBARBH */
- /* Program address for temporary BAR. */ - pci_write_config32(dev, 0x40, 0x40000000); - pci_write_config32(dev, 0x44, 0x0); + /* Activate temporary BAR */ + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5);
- /* Activate temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) | 5); + write16p(THERMAL_BASE + 0x04, 0x3a2b); /* TSTTP */
+ write8p(THERMAL_BASE + 0x0c, 0xff); /* TSES */ + write8p(THERMAL_BASE + 0x0d, 0x00); /* TSGPEN */ + write8p(THERMAL_BASE + 0x0e, 0x40); /* TSPC */ + write8p(THERMAL_BASE + 0x82, 0x00); /* TSPIEN */ + write8p(THERMAL_BASE + 0x01, 0xba); /* TSE */
- write16p (0x40000004, 0x3a2b); - write8p (0x4000000c, 0xff); - write8p (0x4000000d, 0x00); - write8p (0x4000000e, 0x40); - write8p (0x40000082, 0x00); - write8p (0x40000001, 0xba); - - /* Perform init. */ - /* Configure TJmax. */ + /* Perform init */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); - /* Northbridge temperature slope and offset. */ - write16p(0x40000016, 0x808c); + /* Configure TJmax */ + write16p(THERMAL_BASE + 0x12, ((msr.lo >> 16) & 0xff) << 6); /* CTA */
- write16p (0x40000014, 0xde87); + /* Northbridge temperature slope and offset */ + write16p(THERMAL_BASE + 0x16, 0x808c); /* MGTA */
- /* Enable thermal data reporting, processor, PCH and northbridge. */ - write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); + write16p(THERMAL_BASE + 0x14, 0xde87); /* PTA */
- /* Disable temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) & ~1); + /* Enable thermal data reporting, processor, PCH and northbridge in TRC */ + write16p(THERMAL_BASE + 0x1a, (read16p(THERMAL_BASE + 0x1a) & ~0xf) | 0x10f0); + + /* Disable temporary BAR */ + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); pci_write_config32(dev, 0x40, 0);
- write32 (DEFAULT_RCBA + 0x38b0, - (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); + write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); } diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 31aad17..4d8b66a 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -17,43 +17,54 @@ /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, - 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, - 0x20000353 }; + const u32 currents[] = { + 0x20000153, 0x20000f57, 0x2000055b, + 0x20000f51, 0x2000094a, 0x2000035f, + 0x20000f53, 0x20000357, 0x20000353, + }; int i;
- /* Unlock registers. */ + /* Unlock registers */ write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN);
for (i = 0; i < 14; i++) RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current]; + for (i = 0; i < 10; i++) RCBA32(0x3538 + 4 * i) = 0;
for (i = 0; i < 8; i++) RCBA32(0x3560 + 4 * i) = rcba_dump[i]; + for (i = 0; i < 8; i++) RCBA32(0x3580 + 4 * i) = 0; + reg32 = 0; for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); + RCBA32(USBPDO) = reg32; + reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); + RCBA32(USBOCM1) = reg32; + reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); + RCBA32(USBOCM2) = reg32; + for (i = 0; i < 22; i++) RCBA32(0x35a8 + 4 * i) = 0;
- pci_write_config32(PCH_XHCI_DEV, 0xe4, 0x00000000); + pci_write_config32(PCH_XHCI_DEV, 0xe4, 0);
- /* Relock registers. */ + /* Relock registers */ write_pmbase16(UPRWC, 0); } diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index 719f94b..e8431ee 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -9,28 +9,23 @@ #define PCH_EHCI2_TEMP_BAR0 0xe8000400
/* - * Setup USB controller MMIO BAR to prevent the - * reference code from resetting the controller. - * - * The BAR will be re-assigned during device - * enumeration so these are only temporary. + * Setup USB controller MMIO BAR to prevent the reference code from resetting the controller. + * The BAR will be re-assigned during device enumeration so these are only temporary. */ void enable_usb_bar(void) { - pci_devfn_t usb0 = PCH_EHCI1_DEV; - pci_devfn_t usb1 = PCH_EHCI2_DEV; + const pci_devfn_t usb0 = PCH_EHCI1_DEV; + const pci_devfn_t usb1 = PCH_EHCI2_DEV; u32 cmd;
/* USB Controller 1 */ - pci_write_config32(usb0, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); + pci_write_config32(usb0, PCI_BASE_ADDRESS_0, PCH_EHCI1_TEMP_BAR0); cmd = pci_read_config32(usb0, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb0, PCI_COMMAND, cmd);
/* USB Controller 2 */ - pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI2_TEMP_BAR0); + pci_write_config32(usb1, PCI_BASE_ADDRESS_0, PCH_EHCI2_TEMP_BAR0); cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd); diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index dc5da79..4e5edc2 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -13,7 +13,7 @@
void pch_log_state(void) { - u16 pm1_sts, gen_pmcon_3, tco2_sts; + u16 tco2_sts, pm1_sts, gen_pmcon_3; u32 gpe0_sts, gpe0_en; u8 gen_pmcon_2; int i; @@ -21,11 +21,11 @@ if (!lpc) return;
- pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); - gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); + gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); - gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); + gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
/* PWR_FLR Power Failure */ @@ -62,8 +62,7 @@
/* ACPI Wake */ if (pm1_sts & (1 << 15)) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, acpi_is_wakeup_s3() ? 3 : 5);
/* * Wake sources diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 3b6c030..803acf8 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -41,15 +41,14 @@ u32 reg32;
/* Assign unique bus/dev/fn for I/O APIC */ - pci_write_config16(dev, LPC_IBDF, - PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); + pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
/* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
set_ioapic_id(VIO_APIC_VADDR, 0x02);
- /* affirm full set of redirection table entries ("write once") */ + /* Affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
@@ -63,11 +62,10 @@ static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + #if !CONFIG(SERIRQ_CONTINUOUS_MODE) - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif }
@@ -88,6 +86,7 @@ * 0x0D - 1101 = Reserved * 0x0E - 1110 = IRQ14 * 0x0F - 1111 = IRQ15 + * * PIRQ[n]_ROUT[7] - PIRQ Routing Control * 0x80 - The PIRQ is not routed. */ @@ -95,12 +94,12 @@ static void pch_pirq_init(struct device *dev) { struct device *irq_dev; - /* Interrupt 11 is not used by legacy devices and so can always be used for - PCI interrupts. Full legacy IRQ routing is complicated and hard to - get right. Fortunately all modern OS use MSI and so it's not that big of - an issue anyway. Still we have to provide a reasonable default. Using - interrupt 11 for it everywhere is a working default. ACPI-aware OS can - move it to any interrupt and others will just leave them at default. + /* + * Interrupt 11 is not used by legacy devices, so it can always be used for PCI devices. + * Full legacy IRQ routing is complicated and hard to get right. Fortunately, all modern + * OSes use MSI, so it's not that big of an issue anyway. Even then, we have to provide + * a reasonable default. Using interrupt 11 everywhere is a working default, because + * ACPI-aware OSes can move it to any interrupt and others will leave them at default. */ const u8 pirq_routing = 11;
@@ -135,19 +134,17 @@ config_t *config = dev->chip_info; u32 reg32 = 0;
- /* An array would be much nicer here, or some - * other method of doing this. - */ - reg32 |= (config->gpi0_routing & 0x03) << 0; - reg32 |= (config->gpi1_routing & 0x03) << 2; - reg32 |= (config->gpi2_routing & 0x03) << 4; - reg32 |= (config->gpi3_routing & 0x03) << 6; - reg32 |= (config->gpi4_routing & 0x03) << 8; - reg32 |= (config->gpi5_routing & 0x03) << 10; - reg32 |= (config->gpi6_routing & 0x03) << 12; - reg32 |= (config->gpi7_routing & 0x03) << 14; - reg32 |= (config->gpi8_routing & 0x03) << 16; - reg32 |= (config->gpi9_routing & 0x03) << 18; + /* An array would be much nicer here, or some other method of doing this */ + reg32 |= (config->gpi0_routing & 0x03) << 0; + reg32 |= (config->gpi1_routing & 0x03) << 2; + reg32 |= (config->gpi2_routing & 0x03) << 4; + reg32 |= (config->gpi3_routing & 0x03) << 6; + reg32 |= (config->gpi4_routing & 0x03) << 8; + reg32 |= (config->gpi5_routing & 0x03) << 10; + reg32 |= (config->gpi6_routing & 0x03) << 12; + reg32 |= (config->gpi7_routing & 0x03) << 14; + reg32 |= (config->gpi8_routing & 0x03) << 16; + reg32 |= (config->gpi9_routing & 0x03) << 18; reg32 |= (config->gpi10_routing & 0x03) << 20; reg32 |= (config->gpi11_routing & 0x03) << 22; reg32 |= (config->gpi12_routing & 0x03) << 24; @@ -170,11 +167,12 @@ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
- /* Which state do we want to goto after g3 (power restored)? + /* + * Which state do we want to go to after exiting G3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off * - * If the option is not existent (Laptops), use Kconfig setting. + * If the option is not set, use Kconfig setting. */ get_option(&pwr_on, "power_on_after_fail");
@@ -198,12 +196,12 @@ }
reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ - reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
reg16 &= ~(1 << 10); - reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
- reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); @@ -232,15 +230,14 @@ reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~(3 << 0); // SMI# rate 1 minute reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME + #if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using - * periodic SMIs. - */ - reg16 |= (3 << 0); // Periodic SMI every 8s + /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs. */ + reg16 |= (3 << 0); // Periodic SMI every 8s #endif pci_write_config16(dev, GEN_PMCON_1, reg16);
- // Set the board's GPI routing. + /* Set the board's GPI routing */ pch_gpi_routing(dev);
pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -249,14 +246,14 @@ outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
/* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT - reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 0); // SCI_EN + reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04);
/* Clear magic status bits to prevent unexpected wake */ reg32 = RCBA32(PRSTS); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); + reg32 |= (1 << 4) | (1 << 5) | (1 << 0); RCBA32(PRSTS) = reg32;
reg32 = RCBA32(0x3f02); @@ -264,7 +261,7 @@ RCBA32(0x3f02) = reg32; }
-/* CougarPoint PCH Power Management init */ +/* Cougar Point PCH Power Management init */ static void cpt_pm_init(struct device *dev) { printk(BIOS_DEBUG, "CougarPoint PM init\n"); @@ -306,23 +303,23 @@ RCBA32_AND_OR(0x21b0, ~0UL, 0xf); }
-/* PantherPoint PCH Power Management init */ +/* Panther Point PCH Power Management init */ static void ppt_pm_init(struct device *dev) { printk(BIOS_DEBUG, "PantherPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); RCBA32_AND_OR(CIR30, ~0UL, (1 << 0)); RCBA32_AND_OR(CIR5, ~0UL, (1 << 0)); - RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(CIR3, ~0UL, (1 << 13) | (1 << 14)); RCBA16_AND_OR(CIR2, ~0UL, (1 << 14)); RCBA32(DMC) = 0xc03b8400; - RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(CIR6, ~0UL, (1 << 5) | (1 << 18)); + RCBA32_AND_OR(CIR9, ~0UL, (1 << 15) | (1 << 1)); RCBA32_AND_OR(CIR7, ~0x1f, 0xf); RCBA32(PM_CFG) = 0x054f0000; RCBA32(CIR8) = 0x04000000; RCBA32_AND_OR(CIR10, ~0UL, 0xfffff); - RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)|(1 << 0)); + RCBA32_AND_OR(CIR11, ~0UL, (1 << 1) | (1 << 0)); RCBA32(CIR12) = 0x0001c000; RCBA32(CIR14) = 0x00061100; RCBA32(CIR15) = 0x7f8fdfff; @@ -361,7 +358,7 @@
/* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable + reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; } @@ -377,10 +374,10 @@ reg16 |= (1 << 2) | (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16);
- pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(0xeb007f07, ~0UL, (1 << 31)); + pch_iobp_update(0xeb004000, ~0UL, (1 << 7)); + pch_iobp_update(0xec007f07, ~0UL, (1 << 31)); + pch_iobp_update(0xec004000, ~0UL, (1 << 7));
reg32 = RCBA32(CG); reg32 |= (1 << 31); @@ -434,7 +431,7 @@ * Enable DMI ASPM in the PCH */ RCBA32_AND_OR(DMC, ~(1 << 10), 0); - RCBA32_OR(LCAP, (1 << 11)|(1 << 10)); + RCBA32_OR(LCAP, (1 << 11) | (1 << 10)); RCBA32_OR(LCTL, 0x3); }
@@ -446,6 +443,7 @@
if (config->spi_uvscc) RCBA32(0x3800 + 0xc8) = config->spi_uvscc; + if (config->spi_lvscc) RCBA32(0x3800 + 0xc4) = config->spi_lvscc;
@@ -457,51 +455,51 @@ u16 dev_id; const char *dev_name; } pch_table[] = { - /* 6-series PCI ids from - * Intel® 6 Series Chipset and - * Intel® C200 Series Chipset - * Specification Update - NDA + /* + * 6-series PCI IDs from: + * Intel® 6 Series Chipset and Intel® C200 Series Chipset Specification Update - NDA * October 2013 * CDI / IBP#: 440377 */ - {0x1C41, "SFF Sample"}, - {0x1C42, "Desktop Sample"}, - {0x1C43, "Mobile Sample"}, - {0x1C44, "Z68"}, - {0x1C46, "P67"}, - {0x1C47, "UM67"}, - {0x1C49, "HM65"}, - {0x1C4A, "H67"}, - {0x1C4B, "HM67"}, - {0x1C4C, "Q65"}, - {0x1C4D, "QS67"}, - {0x1C4E, "Q67"}, - {0x1C4F, "QM67"}, - {0x1C50, "B65"}, - {0x1C52, "C202"}, - {0x1C54, "C204"}, - {0x1C56, "C206"}, - {0x1C5C, "H61"}, - /* 7-series PCI ids from Intel document 472178 */ - {0x1E41, "Desktop Sample"}, - {0x1E42, "Mobile Sample"}, - {0x1E43, "SFF Sample"}, - {0x1E44, "Z77"}, - {0x1E45, "H71"}, - {0x1E46, "Z75"}, - {0x1E47, "Q77"}, - {0x1E48, "Q75"}, - {0x1E49, "B75"}, - {0x1E4A, "H77"}, - {0x1E53, "C216"}, - {0x1E55, "QM77"}, - {0x1E56, "QS77"}, - {0x1E58, "UM77"}, - {0x1E57, "HM77"}, - {0x1E59, "HM76"}, - {0x1E5D, "HM75"}, - {0x1E5E, "HM70"}, - {0x1E5F, "NM70"}, + {0x1c41, "SFF Sample"}, + {0x1c42, "Desktop Sample"}, + {0x1c43, "Mobile Sample"}, + {0x1c44, "Z68"}, + {0x1c46, "P67"}, + {0x1c47, "UM67"}, + {0x1c49, "HM65"}, + {0x1c4a, "H67"}, + {0x1c4b, "HM67"}, + {0x1c4c, "Q65"}, + {0x1c4d, "QS67"}, + {0x1c4e, "Q67"}, + {0x1c4f, "QM67"}, + {0x1c50, "B65"}, + {0x1c52, "C202"}, + {0x1c54, "C204"}, + {0x1c56, "C206"}, + {0x1c5c, "H61"}, + + /* 7-series PCI IDs from Intel document 472178 */ + {0x1e41, "Desktop Sample"}, + {0x1e42, "Mobile Sample"}, + {0x1e43, "SFF Sample"}, + {0x1e44, "Z77"}, + {0x1e45, "H71"}, + {0x1e46, "Z75"}, + {0x1e47, "Q77"}, + {0x1e48, "Q75"}, + {0x1e49, "B75"}, + {0x1e4a, "H77"}, + {0x1e53, "C216"}, + {0x1e55, "QM77"}, + {0x1e56, "QS77"}, + {0x1e58, "UM77"}, + {0x1e57, "HM77"}, + {0x1e59, "HM76"}, + {0x1e5d, "HM75"}, + {0x1e5e, "HM70"}, + {0x1e5f, "NM70"}, };
static void report_pch_info(struct device *dev) @@ -543,10 +541,10 @@
/* Initialize power management */ switch (pch_silicon_type()) { - case PCH_TYPE_CPT: /* CougarPoint */ + case PCH_TYPE_CPT: /* Cougar Point */ cpt_pm_init(dev); break; - case PCH_TYPE_PPT: /* PantherPoint */ + case PCH_TYPE_PPT: /* Panther Point */ ppt_pm_init(dev); break; default: @@ -583,69 +581,66 @@ pch_spi_init(dev); }
+#define ASSIGNED_FIXED (IORESOURCE_ASSIGNED | IORESOURCE_FIXED) static void pch_lpc_read_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; u8 io_index = 0;
- /* Get the normal PCI resources of this device. */ + /* Get the normal PCI resources of this device */ pci_dev_read_resources(dev);
- /* Add an extra subtractive resource for both memory and I/O. */ + /* Add an extra subtractive resource for both memory and I/O */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0; res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0xff000000; - /* Some systems (e.g. X230) have 12 MiB flash. - SPI controller supports up to 2 x 16 MiB of flash but - address map limits this to 16MiB. */ + /* + * Some systems (e.g. X230) have 12 MiB flash. The SPI controller supports + * up to 2 x 16 MiB of flash but address map limits this to 16MiB. + */ res->size = 0x01000000; /* 16 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED;
res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | ASSIGNED_FIXED;
/* Set PCH IO decode ranges if required.*/ if ((config->gen1_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen1_dec & 0xFFFC; res->size = (config->gen1_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; }
if ((config->gen2_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen2_dec & 0xFFFC; res->size = (config->gen2_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; }
if ((config->gen3_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen3_dec & 0xFFFC; res->size = (config->gen3_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; }
if ((config->gen4_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = config->gen4_dec & 0xFFFC; res->size = (config->gen4_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | ASSIGNED_FIXED; } } +#undef ASSIGNED_FIXED
static void pch_lpc_enable(struct device *dev) { @@ -682,7 +677,7 @@ /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL);
- /* Add it to DSDT. */ + /* Add it to DSDT */ acpigen_write_scope("\"); acpigen_write_name_dword("NVSA", (u32) gnvs); acpigen_pop_len(); @@ -746,6 +741,7 @@ ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + if (chip->docking_supported) { fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } @@ -839,15 +835,12 @@
/* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { - if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || - acpi_is_wakeup_s3()) { + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) outb(APM_CNT_FINALIZE, APM_CNT); - } } }
-void intel_southbridge_override_spi( - struct intel_swseq_spi_config *spi_config) +void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) { struct device *dev = pcidev_on_root(0x1f, 0);
@@ -883,10 +876,9 @@ };
-/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and - * Intel C200 Series Chipset +/* + * IDs for LPC device of Intel 6 Series, Intel 7 Series, and Intel C200 Series Chipsets */ - static const unsigned short pci_device_ids[] = { 0x1c40, 0x1c41, 0x1c42, 0x1c43, 0x1c44, 0x1c45, 0x1c46, 0x1c47, 0x1c48, 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c51, @@ -898,7 +890,8 @@ 0x1e53, 0x1e54, 0x1e55, 0x1e56, 0x1e57, 0x1e58, 0x1e59, 0x1e5a, 0x1e5b, 0x1e5c, 0x1e5d, 0x1e5e, 0x1e5f,
- 0 }; + 0 +};
static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b1f3bfe..2816f90 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -2,11 +2,10 @@ /* This file is part of the coreboot project. */
/* - * This is a ramstage driver for the Intel Management Engine found in the - * 6-series chipset. It handles the required boot-time messages over the - * MMIO-based Management Engine Interface to tell the ME that the BIOS is - * finished with POST. Additional messages are defined for debug but are - * not used unless the console loglevel is high enough. + * This is a ramstage driver for the Intel Management Engine found in the 6-series chipset. + * It handles the required boot-time messages over the MMIO-based Management Engine Interface + * to tell the ME that the BIOS is finished with POST. Additional messages are defined for + * debug but are not used unless the console loglevel is high enough. */
#include <arch/acpi.h> @@ -78,7 +77,6 @@ /* * ME/MEI access helpers using memcpy to avoid aliasing. */ - static inline void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + (offset/sizeof(u32))); @@ -235,8 +233,8 @@ return mei_wait_for_me_ready(); }
-static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *rsp_data, int rsp_bytes) +static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, void *rsp_data, + int rsp_bytes) { struct mei_header mei_rsp; struct mkhi_header mkhi_rsp; @@ -259,12 +257,13 @@ read_me_csr(&me); if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) break; + udelay(ME_DELAY); } if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n", + expected, me.buffer_write_ptr - me.buffer_read_ptr); + return -1; }
@@ -279,6 +278,7 @@ ndata = mei_rsp.length >> 2; if (mei_rsp.length & 3) ndata++; + if (ndata != (expected - 1)) { printk(BIOS_ERR, "ME: response is missing data\n"); return -1; @@ -286,21 +286,21 @@
/* Read and verify MKHI response header from the ME */ mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); - if (!mkhi_rsp.is_response || - mkhi->group_id != mkhi_rsp.group_id || + if (!mkhi_rsp.is_response || mkhi->group_id != mkhi_rsp.group_id || mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); + printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, command %u ?= %u, " + "is_response %u\n", mkhi->group_id, mkhi_rsp.group_id, mkhi->command, + mkhi_rsp.command, mkhi_rsp.is_response); + return -1; } ndata--; /* MKHI header has been read */
/* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); + return -1; }
@@ -318,13 +318,15 @@ return mei_wait_for_me_ready(); }
-static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) +static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data, + void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; + if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0) return -1; + return 0; }
@@ -385,8 +387,7 @@
static inline void print_cap(const char *name, int state) { - printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", - name, state ? "en" : "dis"); + printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", name, state ? "en" : "dis"); }
/* Get ME Firmware Capabilities */ @@ -411,24 +412,22 @@ return -1; }
- print_cap("Full Network manageability", cap.caps_sku.full_net); - print_cap("Regular Network manageability", cap.caps_sku.std_net); - print_cap("Manageability", cap.caps_sku.manageability); - print_cap("Small business technology", cap.caps_sku.small_business); - print_cap("Level III manageability", cap.caps_sku.l3manageability); - print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", - cap.caps_sku.intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", - cap.caps_sku.intel_mpc); - print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); - print_cap("IPV6", cap.caps_sku.ipv6); - print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); - print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan); - print_cap("TLS", cap.caps_sku.tls); - print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan); + print_cap("Full Network manageability", cap.caps_sku.full_net); + print_cap("Regular Network manageability", cap.caps_sku.std_net); + print_cap("Manageability", cap.caps_sku.manageability); + print_cap("Small business technology", cap.caps_sku.small_business); + print_cap("Level III manageability", cap.caps_sku.l3manageability); + print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap.caps_sku.intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); + print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("IPV6", cap.caps_sku.ipv6); + print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); + print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan); + print_cap("TLS", cap.caps_sku.tls); + print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan);
return 0; } @@ -473,8 +472,7 @@ struct me_hfs hfs; u32 reg32;
- mei_base_address = (u32 *) - (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) @@ -485,8 +483,7 @@ memcpy(&hfs, ®32, sizeof(u32));
/* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || + if (hfs.fpt_bad || hfs.working_state != ME_HFS_CWS_NORMAL || hfs.operation_mode != ME_HFS_MODE_NORMAL) return;
@@ -495,8 +492,7 @@
/* Make sure IO is disabled */ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */ @@ -578,8 +574,7 @@ .current_state = gmes.current_state, }; elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); - elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, - &data, sizeof(data)); + elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, &data, sizeof(data)); }
return path; @@ -699,8 +694,7 @@ }
/* - * Leave the ME unlocked in this path. - * It will be locked via SMI command later. + * Leave the ME unlocked in this path. It will be locked via SMI command later. */ break;
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 054c29f..d78802c 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -44,7 +44,6 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address;
- static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -144,6 +143,7 @@ read_me_csr(&me); if (me.ready) return 0; + udelay(ME_DELAY); }
@@ -207,7 +207,7 @@
/* * This implementation does not handle splitting large messages - * across multiple transactions. Ensure the requested length + * across multiple transactions. Ensure the requested length * will fit in the available circular buffer depth. */ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { @@ -238,8 +238,7 @@ return mei_wait_for_me_ready(); }
-static int mei_recv_msg(struct mkhi_header *mkhi, - void *rsp_data, int rsp_bytes) +static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) { struct mei_header mei_rsp; struct mkhi_header mkhi_rsp; @@ -255,7 +254,7 @@
/* * The interrupt status bit does not appear to indicate that the - * message has actually been received. Instead we wait until the + * message has actually been received. Instead we wait until the * expected number of dwords are present in the circular buffer. */ for (n = ME_RETRY; n; --n) { @@ -265,9 +264,8 @@ udelay(ME_DELAY); } if (!n) { - printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n", + expected, me.buffer_write_ptr - me.buffer_read_ptr); return -1; }
@@ -282,6 +280,7 @@ ndata = mei_rsp.length >> 2; if (mei_rsp.length & 3) ndata++; + if (ndata != (expected - 1)) { printk(BIOS_ERR, "ME: response is missing data %d != %d\n", ndata, (expected - 1)); @@ -290,21 +289,20 @@
/* Read and verify MKHI response header from the ME */ mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); - if (!mkhi_rsp.is_response || - mkhi->group_id != mkhi_rsp.group_id || + if (!mkhi_rsp.is_response || mkhi->group_id != mkhi_rsp.group_id || mkhi->command != mkhi_rsp.command) { - printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); + printk(BIOS_ERR, "ME: invalid response, group %u ?= %u,command %u ?= %u, " + "is_response %u\n", mkhi->group_id, mkhi_rsp.group_id, mkhi->command, + mkhi_rsp.command, mkhi_rsp.is_response); return -1; } ndata--; /* MKHI header has been read */
/* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); + return -1; }
@@ -322,11 +320,12 @@ return mei_wait_for_me_ready(); }
-static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) +static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, void *req_data, + void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; + if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) return -1; return 0; @@ -334,8 +333,7 @@
static inline void print_cap(const char *name, int state) { - printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", - name, state ? " en" : "dis"); + printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", name, state ? " en" : "dis"); }
static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) @@ -385,22 +383,22 @@ return; }
- print_cap("Full Network manageability", cap->full_net); - print_cap("Regular Network manageability", cap->std_net); - print_cap("Manageability", cap->manageability); - print_cap("Small business technology", cap->small_business); - print_cap("Level III manageability", cap->l3manageability); - print_cap("IntelR Anti-Theft (AT)", cap->intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); - print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); - print_cap("IPV6", cap->ipv6); - print_cap("KVM Remote Control (KVM)", cap->kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap->och); - print_cap("Virtual LAN (VLAN)", cap->vlan); - print_cap("TLS", cap->tls); - print_cap("Wireless LAN (WLAN)", cap->wlan); + print_cap("Full Network manageability", cap->full_net); + print_cap("Regular Network manageability", cap->std_net); + print_cap("Manageability", cap->manageability); + print_cap("Small business technology", cap->small_business); + print_cap("Level III manageability", cap->l3manageability); + print_cap("IntelR Anti-Theft (AT)", cap->intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); + print_cap("ICC Over Clocking", cap->icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("IPV6", cap->ipv6); + print_cap("KVM Remote Control (KVM)", cap->kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap->och); + print_cap("Virtual LAN (VLAN)", cap->vlan); + print_cap("TLS", cap->tls); + print_cap("Wireless LAN (WLAN)", cap->wlan); }
#if CONFIG(CHROMEOS) && 0 /* DISABLED */ @@ -469,8 +467,7 @@ struct me_hfs hfs; u32 reg32;
- mei_base_address = (void *) - (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + mei_base_address = (void *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) @@ -481,8 +478,7 @@ memcpy(&hfs, ®32, sizeof(u32));
/* Abort and leave device alone if not normal mode */ - if (hfs.fpt_bad || - hfs.working_state != ME_HFS_CWS_NORMAL || + if (hfs.fpt_bad || hfs.working_state != ME_HFS_CWS_NORMAL || hfs.operation_mode != ME_HFS_MODE_NORMAL) return;
@@ -491,8 +487,7 @@
/* Make sure IO is disabled */ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */ @@ -566,8 +561,7 @@ .current_state = gmes.current_state, }; elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); - elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, - &data, sizeof(data)); + elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, &data, sizeof(data)); }
return path; @@ -703,8 +697,7 @@ }
/* - * Leave the ME unlocked in this path. - * It will be locked via SMI command later. + * Leave the ME unlocked in this path. It will be locked via SMI command later. */ break;
@@ -763,10 +756,8 @@ (csr.buffer_depth - 1); } #endif -/* - * mbp seems to be following its own flow, let's retrieve it in a dedicated - * function. - */ + +/* mbp seems to be following its own flow, let's retrieve it in a dedicated function */ static int __unused intel_me_read_mbp(me_bios_payload *mbp_data) { mbp_header mbp_hdr; diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index a19fc01..9ecfc28 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -5,56 +5,56 @@ #include "me.h"
/* HFS1[3:0] Current Working State Values */ -static const char *me_cws_values[] = { +static const char *me_cws_strs[] = { [ME_HFS_CWS_RESET] = "Reset", [ME_HFS_CWS_INIT] = "Initializing", [ME_HFS_CWS_REC] = "Recovery", [ME_HFS_CWS_NORMAL] = "Normal", [ME_HFS_CWS_WAIT] = "Platform Disable Wait", [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", };
/* HFS1[8:6] Current Operation State Values */ -static const char *me_opstate_values[] = { +static const char *me_opstate_strs[] = { [ME_HFS_STATE_PREBOOT] = "Preboot", [ME_HFS_STATE_M0_UMA] = "M0 with UMA", [ME_HFS_STATE_M3] = "M3 without UMA", [ME_HFS_STATE_M0] = "M0 without UMA", [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error", };
/* HFS[19:16] Current Operation Mode Values */ -static const char *me_opmode_values[] = { +static const char *me_opmode_strs[] = { [ME_HFS_MODE_NORMAL] = "Normal", [ME_HFS_MODE_DEBUG] = "Debug or Disabled by AltDisableBit", [ME_HFS_MODE_DIS] = "Soft Temporary Disable", [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message", };
/* HFS[15:12] Error Code Values */ -static const char *me_error_values[] = { +static const char *me_error_strs[] = { [ME_HFS_ERROR_NONE] = "No Error", [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" + [ME_HFS_ERROR_DEBUG] = "Debug Failure", };
/* GMES[31:28] ME Progress Code */ -static const char *me_progress_values[] = { +static const char *me_progress_strs[] = { [ME_GMES_PHASE_ROM] = "ROM Phase", [ME_GMES_PHASE_BUP] = "BUP Phase", [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", [ME_GMES_PHASE_POLICY] = "Policy Module", [ME_GMES_PHASE_MODULE] = "Module Loading", [ME_GMES_PHASE_UNKNOWN] = "Unknown", - [ME_GMES_PHASE_HOST] = "Host Communication" + [ME_GMES_PHASE_HOST] = "Host Communication", };
/* GMES[27:24] Power Management Event */ -static const char *me_pmevent_values[] = { +static const char *me_pmevent_strs[] = { [0x00] = "Clean Moff->Mx wake", [0x01] = "Moff->Mx wake after an error", [0x02] = "Clean global reset", @@ -67,17 +67,17 @@ [0x09] = "Non-power cycle reset", [0x0a] = "Power cycle reset through M3", [0x0b] = "Power cycle reset through Moff", - [0x0c] = "Sx/Mx->Sx/Moff" + [0x0c] = "Sx/Mx->Sx/Moff", };
/* Progress Code 0 states */ -static const char *me_progress_rom_values[] = { +static const char *me_progress_rom_strs[] = { [0x00] = "BEGIN", - [0x06] = "DISABLE" + [0x06] = "DISABLE", };
/* Progress Code 1 states */ -static const char *me_progress_bup_values[] = { +static const char *me_progress_bup_strs[] = { [0x00] = "Initialization starts", [0x01] = "Disable the host wake event", [0x04] = "Flow determination start process", @@ -105,7 +105,7 @@ };
/* Progress Code 3 states */ -static const char *me_progress_policy_values[] = { +static const char *me_progress_policy_strs[] = { [0x00] = "Entery into Policy Module", [0x03] = "Received S3 entry", [0x04] = "Received S4 entry", @@ -128,53 +128,41 @@ if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) return;
+#define PRINT_ME(...) printk(BIOS_DEBUG, __VA_ARGS__) /* Check Current States */ - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); - printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); - printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); - printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); - printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); - printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[gmes->progress_code]); - printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[gmes->current_pmevent]); + PRINT_ME("ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); + PRINT_ME("ME: Bringup Loader Failure : %s\n", hfs->ft_bup_ld_flr ? "YES" : "NO"); + PRINT_ME("ME: Firmware Init Complete : %s\n", hfs->fw_init_complete ? "YES" : "NO"); + PRINT_ME("ME: Manufacturing Mode : %s\n", hfs->mfg_mode ? "YES" : "NO"); + PRINT_ME("ME: Boot Options Present : %s\n", hfs->boot_options_present ? "YES" : "NO"); + PRINT_ME("ME: Update In Progress : %s\n", hfs->update_in_progress ? "YES" : "NO"); + PRINT_ME("ME: Current Working State : %s\n", me_cws_strs[hfs->working_state]); + PRINT_ME("ME: Current Operation State : %s\n", me_opstate_strs[hfs->operation_state]); + PRINT_ME("ME: Current Operation Mode : %s\n", me_opmode_strs[hfs->operation_mode]); + PRINT_ME("ME: Error Code : %s\n", me_error_strs[hfs->error_code]); + PRINT_ME("ME: Progress Phase : %s\n", me_progress_strs[gmes->progress_code]); + PRINT_ME("ME: Power Management Event : %s\n", me_pmevent_strs[gmes->current_pmevent]); + PRINT_ME("ME: Progress Phase State : "); +#undef PRINT_ME
- printk(BIOS_DEBUG, "ME: Progress Phase State : "); switch (gmes->progress_code) { case ME_GMES_PHASE_ROM: /* ROM Phase */ - printk(BIOS_DEBUG, "%s", - me_progress_rom_values[gmes->current_state]); + printk(BIOS_DEBUG, "%s", me_progress_rom_strs[gmes->current_state]); break;
case ME_GMES_PHASE_BUP: /* Bringup Phase */ - if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[gmes->current_state]) + if (gmes->current_state < ARRAY_SIZE(me_progress_bup_strs) + && me_progress_bup_strs[gmes->current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[gmes->current_state]); + me_progress_bup_strs[gmes->current_state]); else printk(BIOS_DEBUG, "0x%02x", gmes->current_state); break;
case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ - if (gmes->current_state < ARRAY_SIZE(me_progress_policy_values) - && me_progress_policy_values[gmes->current_state]) - printk(BIOS_DEBUG, "%s", - me_progress_policy_values[gmes->current_state]); + if (gmes->current_state < ARRAY_SIZE(me_progress_policy_strs) + && me_progress_policy_strs[gmes->current_state]) + printk(BIOS_DEBUG, "%s", me_progress_policy_strs[gmes->current_state]); else printk(BIOS_DEBUG, "0x%02x", gmes->current_state); break; diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 254c5b2..650010b 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -67,26 +67,26 @@ u16 rsvd14[3]; u8 ndid; /* 0x46 - number of device ids */ u32 did[5]; /* 0x47 - 5b device id 1..5 */ - u8 rsvd5[0x9]; + u8 rsvd5[9]; /* Backlight Control */ u8 blcs; /* 0x64 - Backlight Control possible */ u8 brtl; u8 odds; - u8 rsvd6[0x7]; + u8 rsvd6[7]; /* Ambient Light Sensors*/ u8 alse; /* 0x6e - ALS enable */ u8 alaf; u8 llow; u8 lhih; - u8 rsvd7[0x6]; + u8 rsvd7[6]; /* Extended Mobile Access */ u8 emae; /* 0x78 - EMA enable */ u16 emap; /* 0x79 - EMA pointer */ u16 emal; /* 0x7a - EMA Length */ - u8 rsvd8[0x5]; + u8 rsvd8[5]; /* MEF */ u8 mefe; /* 0x82 - MEF enable */ - u8 rsvd9[0x9]; + u8 rsvd9[9]; /* TPM support */ u8 tpmp; /* 0x8c - TPM */ u8 tpme; diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index cb31880..122fd80 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -52,6 +52,7 @@ /* CougarPoint minimum revision */ if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) return 1; + /* PantherPoint any revision */ if (cur_type == PCH_TYPE_PPT) return 1; @@ -96,6 +97,7 @@ RCBA32(IOBPS) = IOBPS_RW_BX; else RCBA32(IOBPS) = IOBPS_READ_AX; + if (!iobp_poll()) return;
@@ -119,6 +121,7 @@ RCBA32(IOBPS) = IOBPS_RW_BX; else RCBA32(IOBPS) = IOBPS_WRITE_AX; + if (!iobp_poll()) return;
@@ -203,19 +206,15 @@
printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev));
- /* Go through static device tree list of devices - * because enumeration is still in progress */ + /* Go through static device tree list because enumeration is still in progress */ for (port = all_devices; port; port = port->next) { /* Only care about PCIe root ports */ - if (PCI_SLOT(port->path.pci.devfn) != - PCI_SLOT(dev->path.pci.devfn)) + if (PCI_SLOT(port->path.pci.devfn) != PCI_SLOT(dev->path.pci.devfn)) continue;
/* Check if port is in range and enabled */ port_func = PCI_FUNC(port->path.pci.devfn); - if (port_func >= dev_func && - port_func < (dev_func + 4) && - port->enabled) + if (port_func >= dev_func && port_func < (dev_func + 4) && port->enabled) return 1; }
@@ -231,8 +230,7 @@ { u32 old_rpfn = new_rpfn;
- printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", - old_fn, new_fn); + printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", old_fn, new_fn);
new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn));
@@ -242,60 +240,48 @@ }
/* Update devicetree with new Root Port function number assignment */ -static void pch_pcie_devicetree_update( - struct southbridge_intel_bd82x6x_config *config) +static void pch_pcie_devicetree_update(struct southbridge_intel_bd82x6x_config *config) { struct device *dev;
- /* - * hotplug map should also be updated along with their - * corresponding port - */ + /* Hotplug map should also be updated along with their corresponding port */ u8 new_hotplug_map[sizeof(config->pcie_hotplug_map)];
/* * Slots that didn't move need the hotplug setting copied too, * so "new_hotplug_map" is initialized with the values of the old map. */ - memcpy(new_hotplug_map, config->pcie_hotplug_map, - sizeof(new_hotplug_map)); + memcpy(new_hotplug_map, config->pcie_hotplug_map, sizeof(new_hotplug_map));
/* Update the function numbers in the static devicetree */ for (dev = all_devices; dev; dev = dev->next) { u8 new_devfn;
/* Only care about PCH PCIe root ports */ - if (PCI_SLOT(dev->path.pci.devfn) != - PCH_PCIE_DEV_SLOT) + if (PCI_SLOT(dev->path.pci.devfn) != PCH_PCIE_DEV_SLOT) continue;
/* Determine the new devfn for this port */ new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, - RPFN_FNGET(new_rpfn, - PCI_FUNC(dev->path.pci.devfn))); + RPFN_FNGET(new_rpfn, PCI_FUNC(dev->path.pci.devfn)));
if (dev->path.pci.devfn != new_devfn) { - printk(BIOS_DEBUG, - "PCH: PCIe map %02x.%1x -> %02x.%1x\n", - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), + printk(BIOS_DEBUG, "PCH: PCIe map %02x.%1x -> %02x.%1x\n", + PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
/* - * Copy the flag to its new position along with - * the corresponding port + * Copy the flag to its new position along with the corresponding port */ new_hotplug_map[PCI_FUNC(new_devfn)] = - config->pcie_hotplug_map - [PCI_FUNC(dev->path.pci.devfn)]; + config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)];
dev->path.pci.devfn = new_devfn; } }
/* Copy the updated map back to its place */ - memcpy(config->pcie_hotplug_map, new_hotplug_map, - sizeof(new_hotplug_map)); + memcpy(config->pcie_hotplug_map, new_hotplug_map, sizeof(new_hotplug_map)); }
/* Special handling for PCIe Root Port devices */ @@ -308,24 +294,22 @@ return;
/* - * Save a copy of the Root Port Function Number map when - * starting to walk the list of PCIe Root Ports so it can - * be updated locally and written out when the last port + * Save a copy of the Root Port Function Number map when starting to walk the list of + * PCIe Root Ports so it can be updated locally and written out when the last port * has been processed. */ if (PCI_FUNC(dev->path.pci.devfn) == 0) { new_rpfn = RCBA32(RPFN);
/* - * Enable Root Port coalescing if the first port is disabled - * or the other devices will not be enumerated by the OS. + * Enable Root Port coalescing if the first port is disabled. + * Otherwise, the other devices will not be enumerated by the OS. */ if (!dev->enabled) config->pcie_port_coalesce = 1;
if (config->pcie_port_coalesce) - printk(BIOS_INFO, - "PCH: PCIe Root Port coalescing is enabled\n"); + printk(BIOS_INFO, "PCH: PCIe Root Port coalescing is enabled\n"); }
if (!dev->enabled) { @@ -360,8 +344,7 @@
/* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32);
/* Do not claim downstream transactions for PCIe ports */ @@ -377,13 +360,12 @@ * port in order to maintain linear order starting at zero. */ if (config->pcie_port_coalesce) { - for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { + for (fn = 0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { if (!(new_rpfn & RPFN_HIDE(fn))) continue;
/* Swap places with this function */ - pch_pcie_function_swap( - PCI_FUNC(dev->path.pci.devfn), fn); + pch_pcie_function_swap(PCI_FUNC(dev->path.pci.devfn), fn); break; } } @@ -399,8 +381,7 @@ * update the Root Port Function Number and Hide register. */ if (PCI_FUNC(dev->path.pci.devfn) == 7) { - printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - RCBA32(RPFN), new_rpfn); + printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", RCBA32(RPFN), new_rpfn); RCBA32(RPFN) = new_rpfn;
/* Update static devictree with new function numbers */ @@ -422,8 +403,7 @@
/* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32);
/* Hide this device if possible */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 18383f6..88b479a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -7,8 +7,8 @@ #include <arch/acpi.h>
/* PCH types */ -#define PCH_TYPE_CPT 0x1c /* CougarPoint */ -#define PCH_TYPE_PPT 0x1e /* IvyBridge */ +#define PCH_TYPE_CPT 0x1c /* Cougar Point */ +#define PCH_TYPE_PPT 0x1e /* Panther Point */
/* PCH stepping values for LPC device */ #define PCH_STEP_A0 0 @@ -19,12 +19,10 @@ #define PCH_STEP_B3 5
/* - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. + * It does not matter where we put the SMBus I/O base, as long as we keep it consistent and + * don't interfere with other devices. Stage2 will relocate this anyway. Our solution is to + * have SMBus initialization move the I/O to SMBUS_IO_BASE again. But handling static BARs + * is a generic problem that should be solved in the device allocator. */ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 @@ -237,7 +235,7 @@ #define PMBASE 0x40
#define CIR0 0x0050 /* 32bit */ -#define TCLOCKDN (1u << 31) +#define TCLOCKDN (1 << 31)
#define RCTCL 0x0100 /* 32bit */ #define ESD 0x0104 /* 32bit */ @@ -381,9 +379,8 @@ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8
-#define DIR_ROUTE(x,a,b,c,d) \ - RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) +#define DIR_ROUTE(x, a, b, c, d) \ + RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | ((b) << DIR_IBR) | ((a) << DIR_IAR))
#define PRSTS 0x3310 /* 32bit */ #define CIR7 0x3314 /* 32bit */ @@ -416,7 +413,7 @@ #define CG 0x341c /* 32bit */
/* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) +#define PCH_DISABLE_ALWAYS ((1 << 0) | (1 << 26)) #define PCH_DISABLE_P2P (1 << 1) #define PCH_DISABLE_SATA1 (1 << 2) #define PCH_DISABLE_SMBUS (1 << 3) @@ -499,7 +496,7 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#define PM2_CNT 0x50 // mobile only +#define PM2_CNT 0x50 /* Mobile only */ #define GPE0_STS 0x20 #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -559,5 +556,5 @@ #define SPIBAR_FADDR 0x3808 /* SPI flash address */ #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */
-#endif /* __ACPI__ */ -#endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ +#endif /* __ACPI__ */ +#endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 459ed46..2183dc6 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -37,7 +37,7 @@
/* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); - //reg16 |= 0xf900; + // reg16 |= 0xf900; pci_write_config16(dev, PSTS, reg16);
reg16 = pci_read_config16(dev, SECSTS); diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index c70e09c..345797b 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -96,7 +96,7 @@ /* Adjust Common Clock exit latency */ reg32 = pci_read_config32(dev, 0xd8); reg32 &= ~(1 << 17); - reg32 |= (1 << 16) | (1 << 15); + reg32 |= (1 << 16) | (1 << 15); reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */ pci_write_config32(dev, 0xd8, reg32);
@@ -215,8 +215,7 @@ reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32);
- /* Set Cache Line Size to 0x10 */ - // This has no effect but the OS might expect it + /* Set Cache Line Size to 0x10. This has no effect but the OS might expect it. */ pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); @@ -237,18 +236,16 @@
/* Clear errors in status registers */ reg16 = pci_read_config16(dev, 0x06); - //reg16 |= 0xf900; + // reg16 |= 0xf900; pci_write_config16(dev, 0x06, reg16);
reg16 = pci_read_config16(dev, 0x1e); - //reg16 |= 0xf900; + // reg16 |= 0xf900; pci_write_config16(dev, 0x1e, reg16);
/* Enable expresscard hotplug events. */ if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { - pci_write_config32(dev, 0xd8, - pci_read_config32(dev, 0xd8) - | (1 << 30)); + pci_write_config32(dev, 0xd8, pci_read_config32(dev, 0xd8) | (1 << 30)); pci_write_config16(dev, 0x42, 0x142); } } @@ -277,14 +274,9 @@ static const char *pch_pcie_acpi_name(const struct device *dev) { if (dev && PCI_SLOT(dev->path.pci.devfn) == 0x1c) { - static const char *names[] = { "RP01", - "RP02", - "RP03", - "RP04", - "RP05", - "RP06", - "RP07", - "RP08"}; + static const char *names[] = { + "RP01", "RP02", "RP03", "RP04", "RP05", "RP06", "RP07", "RP08", + };
return names[PCI_FUNC(dev->path.pci.devfn)]; } @@ -307,11 +299,12 @@ .ops_pci = &pci_ops, };
-static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16, - 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, - 0x1e10, 0x1e12, 0x1e14, 0x1e16, - 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c10, 0x1c12, 0x1c14, 0x1c16, 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, + 0x1e10, 0x1e12, 0x1e14, 0x1e16, 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, + + 0, +};
static const struct pci_driver pch_pcie __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 3a2ed10..aa32d85 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -63,11 +63,11 @@ pci_write_config8(dev, INTR_LN, 0x0a);
/* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); + + pci_write_config16(dev, IDE_TIM_SEC, + IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
/* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); @@ -79,41 +79,43 @@
/* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; /* 6 ports SKU + ORM */ + reg16 &= ~0x3f; /* 6 ports SKU + ORM */ reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x0183);
/* Initialize AHCI memory-mapped space */ abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ + + /* CAP (HBA Capabilities): enable power management */ reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS + reg32 |= 0x0c006000; /* Set PSC+SSC+SALP+SSS */ + reg32 &= ~0x00020060; /* Clear SXS+EMS+PMS */ + /* Set ISS, if available */ - if (config->sata_interface_speed_support) - { + if (config->sata_interface_speed_support) { reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; + reg32 |= (config->sata_interface_speed_support & 0x03) << 20; } write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + (void) read32(abar + 0x0c); /* Read back 1 */ + (void) read32(abar + 0x0c); /* Read back 2 */ + /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); reg32 &= ~0x00000002; write32(abar + 0x24, reg32); + /* VSP (Vendor Specific Register */ reg32 = read32(abar + 0xa0); reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); + } else { /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); @@ -126,9 +128,7 @@ reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16);
- /* Native mode capable on both primary and secondary (0xa) - * or'ed with enabled (0x50) = 0xf - */ + /* Native mode capable on both primary and secondary or'ed with enabled */ pci_write_config8(dev, 0x09, 0x8f);
/* Set Interrupt Line */ @@ -136,12 +136,11 @@ pci_write_config8(dev, INTR_LN, 0xff);
/* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_SITRE | IDE_ISP_3_CLOCKS | - IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0 | IDE_PPE0); + + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0 | IDE_SITRE);
/* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); @@ -158,8 +157,7 @@ pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x0183); }
/* Set Gen3 Transmitter settings if needed */ @@ -176,12 +174,12 @@ sir_write(dev, 0x28, 0xa0000033); reg32 = sir_read(dev, 0x54); reg32 &= 0xff000000; - reg32 |= 0x5555aa; + reg32 |= 0x005555aa; sir_write(dev, 0x54, reg32); sir_write(dev, 0x64, 0xcccc8484); reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; - reg32 |= 0xcccc; + reg32 |= 0x0000cccc; sir_write(dev, 0x68, reg32); reg32 = sir_read(dev, 0x78); reg32 &= 0x0000ffff; @@ -247,14 +245,16 @@ = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &sata_pci_ops, .acpi_name = sata_acpi_name, };
-static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, - 0x1e00, 0x1e01, 0x1e02, 0x1e03, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c00, 0x1c01, 0x1c02, 0x1c03, 0x1e00, 0x1e01, 0x1e02, 0x1e03, + + 0, +};
static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops, diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 11568b3..3af8555 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -53,12 +53,12 @@ }
static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, };
static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 78ac08b..ec9a3d0 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -30,9 +30,10 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: - * On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 + /* + * gnvs->smif: + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 */ gnvs->smif = 0; return 1; /* IO trap handled */ @@ -42,8 +43,7 @@ return 0; }
-static void southbridge_gate_memory_reset_real(int offset, - u16 use, u16 io, u16 lvl) +static void southbridge_gate_memory_reset_real(int offset, u16 use, u16 io, u16 lvl) { u32 reg32;
@@ -109,8 +109,7 @@ reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
- xhci_bar = pci_read_config32(PCH_XHCI_DEV, - PCI_BASE_ADDRESS_0) & ~0xFUL; + xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xfUL;
if ((xhci_bar + 0x4C0) & 1) pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); @@ -141,15 +140,15 @@ void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; + + u32 trap_sts, trap_cycle, data, mask = 0; int i;
trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { + for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 2)); } @@ -162,8 +161,8 @@ return; }
- /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ + /* IOTRAP(2) currently unused */ + /* IOTRAP(1) currently unused */
/* IOTRAP(0) SMIC */ if (IOTRAP(0)) { @@ -179,7 +178,10 @@ }
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i = 0; i < 4; i++) + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); @@ -200,8 +202,8 @@
void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); + const em64t101_smm_state_save_area_t *state = smi_apmc_find_state_save(apm_cnt); + if (state) { /* EBX in the state save contains the GNVS pointer */ gnvs = (global_nvs_t *)((u32)state->rbx); diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 1d7120d..a6944fc 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -36,7 +36,7 @@ //reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32);
- /* For others, done in MRC. */ + /* For others, done in MRC */ #if CONFIG(USE_NATIVE_RAMINIT) struct resource *res; u8 access_cntl; @@ -50,8 +50,7 @@ if (res) { /* Number of ports and companion controllers. */ reg32 = read32((void *)(uintptr_t)(res->base + 4)); - write32((void *)(uintptr_t)(res->base + 4), - (reg32 & 0xfff00000) | 3); + write32((void *)(uintptr_t)(res->base + 4), (reg32 & 0xfff00000) | 3); }
/* Restore protection. */ @@ -61,19 +60,18 @@ printk(BIOS_DEBUG, "done.\n"); }
-static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { u8 access_cntl;
access_cntl = pci_read_config8(dev, 0x80);
- /* Enable writes to protected registers. */ + /* Enable writes to protected registers */ pci_write_config8(dev, 0x80, access_cntl | 1);
pci_dev_set_subsystem(dev, vendor, device);
- /* Restore protection. */ + /* Restore protection */ pci_write_config8(dev, 0x80, access_cntl); }
@@ -89,7 +87,7 @@ }
static struct pci_operations lops_pci = { - .set_subsystem = &usb_ehci_set_subsystem, + .set_subsystem = &usb_ehci_set_subsystem, };
static struct device_operations usb_ehci_ops = { @@ -97,13 +95,12 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, .acpi_name = usb_ehci_acpi_name, };
-static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, - 0 }; +static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, 0 };
static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops, diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 8696d59..cd81bb8 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -5,10 +5,10 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "pch.h" #include <device/pci_ehci.h> #include <device/pci_ops.h> #include "chip.h" +#include "pch.h"
static void usb_xhci_init(struct device *dev) { @@ -20,7 +20,7 @@ if (config->xhci_overcurrent_mapping) pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping);
- /* lock overcurrent map */ + /* Lock overcurrent map */ reg32 = pci_read_config32(dev, 0x44); reg32 |= 1; pci_write_config32(dev, 0x44, reg32); @@ -31,9 +31,8 @@ /* Enable clock gating */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~((1 << 20) | (1 << 21)); - reg32 |= (1 << 19) | (1 << 18) | (1 << 17); - reg32 |= (1 << 10) | (1 << 9) | (1 << 8); - reg32 |= (1 << 31); /* lock */ + reg32 |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 10) | (1 << 9) | (1 << 8); + reg32 |= (1 << 31); /* lock */ pci_write_config32(dev, 0x40, reg32);
printk(BIOS_DEBUG, "done.\n"); @@ -45,7 +44,7 @@ }
static struct pci_operations xhci_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations usb_xhci_ops = { @@ -53,7 +52,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_xhci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &xhci_pci_ops, .acpi_name = xhci_acpi_name, };
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40020 )
Change subject: sb/intel/bd82x6x: Tidy up code and comments ......................................................................
Patch Set 1:
(13 comments)
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/early_pch.c:
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 144: void early_pch_init_native (void) space prohibited between function name and open parenthesis '('
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/me_status.c:
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 8: static const char *me_cws_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 19: static const char *me_opstate_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 29: static const char *me_opmode_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 38: static const char *me_error_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 46: static const char *me_progress_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 57: static const char *me_pmevent_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 74: static const char *me_progress_rom_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 80: static const char *me_progress_bup_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 108: static const char *me_progress_policy_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 137: PRINT_ME("ME: Boot Options Present : %s\n", hfs->boot_options_present ? "YES" : "NO"); line over 96 characters
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pch.h:
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 382: #define DIR_ROUTE(x, a, b, c, d) \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pcie.c:
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 277: static const char *names[] = { static const char * array should probably be static const char * const
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40020 )
Change subject: sb/intel/bd82x6x: Tidy up code and comments ......................................................................
Patch Set 1:
(2 comments)
Thank you for cleaning this up.
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/smbus.c:
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 56: .read_byte = lsmbus_read_byte, Why not stay with tabs?
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/usb_ehci.c:
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 98: .scan_bus = NULL, Why not `DEVICE_NOOP`?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40020 )
Change subject: sb/intel/bd82x6x: Tidy up code and comments ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/smbus.c:
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 56: .read_byte = lsmbus_read_byte,
Why not stay with tabs?
Because they are completely unnecessary, the alignment difference is a single character.
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/usb_ehci.c:
https://review.coreboot.org/c/coreboot/+/40020/1/src/southbridge/intel/bd82x... PS1, Line 98: .scan_bus = NULL,
Why not `DEVICE_NOOP`?
Paul, that would change the binary.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40020 )
Change subject: sb/intel/bd82x6x: Tidy up code and comments ......................................................................
Patch Set 2:
(13 comments)
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/early_pch.c:
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 144: void early_pch_init_native (void) space prohibited between function name and open parenthesis '('
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/me_status.c:
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 8: static const char *me_cws_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 19: static const char *me_opstate_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 29: static const char *me_opmode_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 38: static const char *me_error_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 46: static const char *me_progress_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 57: static const char *me_pmevent_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 74: static const char *me_progress_rom_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 80: static const char *me_progress_bup_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 108: static const char *me_progress_policy_strs[] = { static const char * array should probably be static const char * const
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 137: PRINT_ME("ME: Boot Options Present : %s\n", hfs->boot_options_present ? "YES" : "NO"); line over 96 characters
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pch.h:
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 382: #define DIR_ROUTE(x, a, b, c, d) \ Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pcie.c:
https://review.coreboot.org/c/coreboot/+/40020/2/src/southbridge/intel/bd82x... PS2, Line 277: static const char *names[] = { static const char * array should probably be static const char * const
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40020 )
Change subject: sb/intel/bd82x6x: Tidy up code and comments ......................................................................
Abandoned
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
-
Paul Menzel (Code Review)