Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Furquan Shaikh (Code Review)]

Attention is currently required from: Bora Guvendik, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Angel Pons, Patrick Rudolph.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: mb/adlrvp: Fix DDR5 Boot issue
......................................................................

Patch Set 19:

(2 comments)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/1b3624c7_c229d848 
PS19, Line 224: spd_addr_array
This is something that is very mainboard specific. Also, `mem_spd` (https://review.coreboot.org/plugins/gitiles/coreboot/+/4676279151659922da871...) already provides a member `addr_dimm` that can be used. Please see comment below.

https://review.coreboot.org/c/coreboot/+/50996/comment/f81999e4_305ce4b2 
PS19, Line 260: smbus_address_valid = true;
DDR5 can be either memory-down or DIMMs. The current limitation is only for mainboards that are using DIMMs since SMBUS driver in coreboot is not yet updated to support DDR5 EEPROMs. Given that I think we should handle this as follows:

```
    /*
     * TODO: Drop this workaround once SMBus driver in coreboot is updated to 
     * support DDR5 EEPROM reading.
     */
    if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
          ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
          return;
    }
```

and the above function can be:

```
#define DDR5_CH_DIMM_OFFSET(ch, dimm)        ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info)
{
      for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) {
            for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
                   size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch];
                   mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] = info->smbus[ch].addr_dimm[dimm];
            }
      }

mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
      mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
}
```

In mainboard, you will have to configure ddr5_spd_info just like you currently do it for ddr4:

```
»       const struct mem_spd ddr5_spd_info = {                                                                                                              
»       »       .topo = MEM_TOPO_DIMM_MODULE,                                                                                                                    
»       »       .smbus = {                                                                                                                                       
»       »       »       [0] = {                                                                                                                                  
»       »       »       »       .addr_dimm[0] = 0xa0,                                                                                                            
»       »       »       »       .addr_dimm[1] = 0xa2,                                                                                                            
»       »       »       },                                                                                                                                       
»       »       »       [2] = {                                                                                                                                  
»       »       »       »       .addr_dimm[0] = 0xa4,                                                                                                            
»       »       »       »       .addr_dimm[1] = 0xa6,                                                                                                            
»       »       »       },                                                                                                                                       
»       »       },                                                                                                                                               
»       };
```

Once SMBus support is added for DDR5, then only the workaround in SoC will have to be dropped. Mainboard code will remain unchanged.