Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44149 )
Change subject: mb/tglrvp: Update SPD files for Hynex ......................................................................
mb/tglrvp: Update SPD files for Hynex
- Increase DDR Frquency limit to support data rate 4266 Mbps
Bug=None Test=Build and boot on tglrvp hardware; $dmidecode --type 17 reflects memory Speed = 4266
Signed-off-by: Anil Kumar anil.kumar.k@intel.com Change-Id: I8185ebbaa32a01fee104bc0b757fc4adb58bba97 --- M src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44149/1
diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex index 2ff9ed3..4bf724e 100644 --- a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex @@ -1,5 +1,5 @@ 23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00 -00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 +00 00 04 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44149 )
Change subject: mb/tglrvp: Update SPD files for Hynex ......................................................................
Patch Set 1: Code-Review+1
Hello Shreesh Chhabbi, Ravishankar Sarawadi, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44149
to look at the new patch set (#2).
Change subject: mb/tglrvp: Update SPD files for Hynix ......................................................................
mb/tglrvp: Update SPD files for Hynix
- Increase DDR Frquency limit to support data rate 4266 Mbps
Bug=None Test=Build and boot on tglrvp hardware; $dmidecode --type 17 reflects memory Speed = 4266
Signed-off-by: Anil Kumar anil.kumar.k@intel.com Change-Id: I8185ebbaa32a01fee104bc0b757fc4adb58bba97 --- M src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44149/2
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44149 )
Change subject: mb/tglrvp: Update SPD files for Hynix ......................................................................
Patch Set 2: Code-Review+1
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44149 )
Change subject: mb/tglrvp: Update SPD files for Hynix ......................................................................
Patch Set 2: Code-Review+2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44149 )
Change subject: mb/tglrvp: Update SPD files for Hynix ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44149 )
Change subject: mb/tglrvp: Update SPD files for Hynix ......................................................................
mb/tglrvp: Update SPD files for Hynix
- Increase DDR Frquency limit to support data rate 4266 Mbps
Bug=None Test=Build and boot on tglrvp hardware; $dmidecode --type 17 reflects memory Speed = 4266
Signed-off-by: Anil Kumar anil.kumar.k@intel.com Change-Id: I8185ebbaa32a01fee104bc0b757fc4adb58bba97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44149 Reviewed-by: Ravishankar Sarawadi ravishankar.sarawadi@intel.corp-partner.google.com Reviewed-by: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Ravishankar Sarawadi: Looks good to me, approved Ravishankar Sarawadi: Looks good to me, but someone else must approve Srinidhi N Kaushik: Looks good to me, approved Anil Kumar K: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex index 2ff9ed3..4bf724e 100644 --- a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex @@ -1,5 +1,5 @@ 23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00 -00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 +00 00 04 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Anil Kumar K (Code Review) -
Patrick Georgi (Code Review)
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Ravishankar Sarawadi (Code Review)
-
Srinidhi N Kaushik (Code Review)