Change in coreboot[master]: soc/intel/alderlake: Enable Intel FIVR RFI settings

[Chen Wisley (Code Review)]

Attention is currently required from: Wisley Chen.
Hello Wisley Chen,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/58878

to review the following change.

Change subject: soc/intel/alderlake: Enable Intel FIVR RFI settings
......................................................................

soc/intel/alderlake: Enable Intel FIVR RFI settings

Add RFI UPD settings to mitigate RFI noise issues  and exporting
these UPDs to override via board devicetree.

BUG=none
TEST=build

Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34
Signed-off-by: Wisley Chen 
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/58878/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 699626b..3bdffd8 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -495,6 +495,22 @@

/* Platform Power Pmax */
    uint16_t PsysPmax;
+	/*
+	 * FivrRfiFrequency
+	 * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
+	 * 0: Auto
+	 * Range varies based on XTAL clock:
+	 *   0-1918 (Up to 191.8HMz) for 24MHz clock
+	 *   0-1535 (Up to 153.5MHz) for 19MHz clock
+	 */
+	uint16_t FivrRfiFrequency;
+	/*
+	 * FivrSpreadSpectrum
+	 * Set the Spread Spectrum Range.
+	 *   Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each Range is translated to an encoded value for FIVR register.
+	 *   0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
+	 */
+	uint8_t FivrSpreadSpectrum;
 };

typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 9ed8acd..fdd1fc6 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -731,6 +731,13 @@
    		config->ext_fivr_settings.vnn_icc_max_ma;
 }

+static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,
+                const struct soc_intel_alderlake_config *config)
+{
+	s_cfg->FivrRfiFrequency = config->FivrRfiFrequency;
+	s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum;
+}
+
 static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
    	struct soc_intel_alderlake_config *config)
 {
@@ -761,6 +768,7 @@
    	fill_fsps_misc_power_params,
    	fill_fsps_irq_params,
    	fill_fsps_fivr_params,
+		fill_fsps_fivr_rfi_params,
    };

for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)