Attention is currently required from: Ashish Kumar Mishra, Subrata Banik.
Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84142?usp=email
to look at the new patch set (#4).
Change subject: src/include/: Introducing a new BIT_32(x) macro.
......................................................................
src/include/: Introducing a new BIT_32(x) macro.
This new macro addition ensures the shift operation does not
exceed the 32-bit width of the GEN_PMCON_A register.
Details-
On a 64-bit system, 1ul will typically be 64 bits wide.
The left shift can accommodate values of x up to 63 without overflowing.
But `GEN_PMCON_A` register width is 32-bit hence, adding new BIT_32(x)
to limit the register to max 32-bit width.
Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com
---
M src/include/types.h
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84142/4
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Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Gerrit-Change-Number: 84142
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