[XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: add ACPI code

[Jonathan Zhang (Code Review)]

Attention is currently required from: Patrick Rudolph, Simon Chou, Johnny Lin, Christian Walter, Shuming Chu (Shuming), Arthur Heymans.

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71967 )

Change subject: soc/intel/xeon_sp/spr: add ACPI code
......................................................................

Patch Set 13:

(2 comments)

File src/soc/intel/xeon_sp/spr/acpi/uncore.asl:

https://review.coreboot.org/c/coreboot/+/71967/comment/b6444edc_fe63a8e6 
PS13, Line 38: 	#if (CONFIG_MAX_SOCKET > 3)
This part of the DSDT code should be generated, using hob->PlatformData.numofIIO.

File src/soc/intel/xeon_sp/spr/soc_acpi.c:

https://review.coreboot.org/c/coreboot/+/71967/comment/f3b8a959_5d348b60 
PS13, Line 387: 	for (uint8_t socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
> The issue is that SSDT needs to be in sync with DSDT (src/soc/intel/xeon_sp/spr/acpi/uncore. […]

Got you. I think we should use hob->PlatformData.numofIIO for DSDT as well; in other words, we should generate that part of the DSDT code. Do you agree?