Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14406
-gerrit
commit 15882ea6e21461068ace3cc74971f4d05b63aae5 Author: Stefan Reinauer stefan.reinauer@coreboot.org Date: Mon Apr 18 18:01:55 2016 -0700
kontron/come-bip2: Configure device tree correctly
Change-Id: I19b3acedebcbf82aa3fd60cd702394099050cd30 Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org --- src/mainboard/kontron/come-bip2/devicetree.cb | 99 ++++++++++++++++----------- 1 file changed, 58 insertions(+), 41 deletions(-)
diff --git a/src/mainboard/kontron/come-bip2/devicetree.cb b/src/mainboard/kontron/come-bip2/devicetree.cb index 437b3cb..5e4e6b6 100644 --- a/src/mainboard/kontron/come-bip2/devicetree.cb +++ b/src/mainboard/kontron/come-bip2/devicetree.cb @@ -1,24 +1,7 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "1" - register "gfx.did" = "{ 0x80000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000 }" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP_A - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" - - register "max_mem_clock_mhz" = "666" + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 @@ -39,8 +22,8 @@ chip northbridge/intel/sandybridge end
device domain 0 on - subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge + device pci 01.0 on end # PCIe Bridge x16 device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH @@ -48,19 +31,18 @@ chip northbridge/intel/sandybridge # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0100" + register "alt_gp_smi_en" = "0x0000" register "gpi7_routing" = "2" register "gpi8_routing" = "1"
- register "sata_port_map" = "0x1" - + # Enable all SATA ports 0-5 + register "sata_port_map" = "0x3f" register "sata_port0_gen3_tx" = "0x00880a7f"
- # EC range is 0x800-0x9ff # Please note: you MUST not change this unless # you also change romstage.c:pch_enable_lpc - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" + register "gen1_dec" = "0x00040291" + register "gen2_dec" = "0x007c0a81"
# Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" @@ -68,31 +50,66 @@ chip northbridge/intel/sandybridge register "c2_latency" = "1" register "p_cnt_throttling_supported" = "0"
+ device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet + device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 (WLAN remapped) - device pci 1c.1 off end # PCIe Port #2 + device pci 1c.0 on end # PCIe Port #1 (WLAN remapped) + device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on end # PCIe Port #3 (WLAN actual) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge + device pci 1e.0 on end # PCI bridge device pci 1f.0 on - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address + chip superio/winbond/w83627dhg + device pnp 2e.0 off # Floppy + end + device pnp 2e.1 off # Parallel Port + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 #keyboard + irq 0x72 = 0x0C #mouse + end + device pnp 2e.6 off # SPI + end + device pnp 2e.307 off # GPIO6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO2 + end + device pnp 2e.109 off # GPIO3 + end + device pnp 2e.209 off # GPIO4 + end + device pnp 2e.309 off # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # HWM + io 0x60 = 0x290 + end + device pnp 2e.c off # PECI, SST end - end + end # superio/winbond/w83627dhg end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on end # SMBus
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Stefan Reinauer