David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46611 )
Change subject: mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF ......................................................................
mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF
Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports
BUG=none BRANCH=master TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46611/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 7486aef..b76f627 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -103,10 +103,10 @@ register "PcieClkSrcClkReq[1]" = "1"
# Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality - register "PcieClkSrcUsage[2]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" - register "PcieClkSrcUsage[6]" = "0xFF" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
# Enable SATA register "SataEnable" = "1"
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46611 )
Change subject: mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF ......................................................................
Patch Set 1: Code-Review+2
Thanks David!
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46611 )
Change subject: mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF ......................................................................
Patch Set 1: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46611 )
Change subject: mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF ......................................................................
mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF
Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports
BUG=none BRANCH=master TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46611 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 7486aef..b76f627 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -103,10 +103,10 @@ register "PcieClkSrcClkReq[1]" = "1"
# Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality - register "PcieClkSrcUsage[2]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" - register "PcieClkSrcUsage[6]" = "0xFF" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
# Enable SATA register "SataEnable" = "1"
-
Angel Pons (Code Review) -
David Wu (Code Review)
-
Patrick Georgi (Code Review)
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Tim Wawrzynczak (Code Review)