Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59082 )
Change subject: mb/google/guybrush: Add variant_espi_gpio_table ......................................................................
mb/google/guybrush: Add variant_espi_gpio_table
Add separate gpio table for early eSPI bus init. Remove espi GPIO from early_gpio_table. This allows for initializing eSPI separately from other GPIOs. Simplify verstage_mainboard_early_init.
BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush
Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes robbarnes@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com Reviewed-by: Kangheui Won khwon@chromium.org --- M src/mainboard/google/guybrush/bootblock.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/verstage.c M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 6 files changed, 64 insertions(+), 42 deletions(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Kangheui Won: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index bffcb0c..1154444 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -31,8 +31,8 @@ void bootblock_mainboard_early_init(void) { uint32_t dword; - size_t base_num_gpios, override_num_gpios; - const struct soc_amd_gpio *base_gpios, *override_gpios; + size_t num_gpios, override_num_gpios; + const struct soc_amd_gpio *gpios, *override_gpios;
/* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped on Picasso and older compared to Renoir/Cezanne and newer */ @@ -50,11 +50,12 @@ if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) return;
- base_gpios = variant_early_gpio_table(&base_num_gpios); - override_gpios = variant_early_override_gpio_table(&override_num_gpios); + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios);
- gpio_configure_pads_with_override(base_gpios, base_num_gpios, - override_gpios, override_num_gpios); + gpios = variant_early_gpio_table(&num_gpios); + override_gpios = variant_early_override_gpio_table(&override_num_gpios); + gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios);
/* Set a timer to make sure there's enough delay for * the Fibocom 350 PCIe init diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index fb01789..6b8c2b7 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -206,10 +206,23 @@ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* GSC_SOC_INT_L */ PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + +/* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + +/* Support EC trusted */ + /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */ + PAD_GPI(GPIO_91, PULL_NONE), +}; + +static const struct soc_amd_gpio espi_gpio_table[] = { + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* ESPI_SOC_CLK */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* ESPI1_DATA0 */ @@ -222,16 +235,6 @@ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), - -/* Enable UART 0 */ - /* UART0_RXD */ - PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), - /* UART0_TXD */ - PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - -/* Support EC trusted */ - /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */ - PAD_GPI(GPIO_91, PULL_NONE), };
/* Power-on timing requirements: @@ -344,3 +347,9 @@ *size = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } + +const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 955d170..0dc6c7b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -40,6 +40,9 @@ /* This function provides GPIO settings before entering sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size);
+/* This function provides GPIO settings for eSPI bus. */ +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); + bool variant_has_pcie_wwan(void);
void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index e6434df..17481d2 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -4,41 +4,45 @@ #include <amdblocks/gpio.h> #include <arch/io.h> #include <baseboard/variants.h> +#include <psp_verstage.h> #include <security/vboot/vboot_common.h> #include <soc/southbridge.h>
-static void setup_gpio(void) +void verstage_mainboard_early_init(void) { const struct soc_amd_gpio *gpios, *override_gpios; size_t num_gpios, override_num_gpios;
- if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - gpios = variant_early_gpio_table(&num_gpios); - override_gpios = variant_early_override_gpio_table(&override_num_gpios); + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return;
- gpio_configure_pads_with_override(gpios, num_gpios, - override_gpios, override_num_gpios); - } + gpios = variant_early_gpio_table(&num_gpios); + override_gpios = variant_early_override_gpio_table(&override_num_gpios); + gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios); }
-void verstage_mainboard_early_init(void) +void verstage_mainboard_espi_init(void) { - setup_gpio(); + const struct soc_amd_gpio *gpios; + size_t num_gpios; + uint32_t dword; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios);
/* - * TODO : Make common function in cezanne code and just call it - * when PCI access is fixed in the PSP (b/186602472). - * For now the PSP doesn't configure LPC so it should be fine. - */ - if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - uint32_t dword; - printk(BIOS_DEBUG, "Verstage configure eSPI\n"); - dword = pm_io_read32(PM_SPI_PAD_PU_PD); - dword |= PM_ESPI_CS_USE_DATA2; - pm_io_write32(PM_SPI_PAD_PU_PD, dword); + * TODO : Make common function in cezanne code and just call it + * when PCI access is fixed in the PSP (b/186602472). + * For now the PSP doesn't configure LPC so it should be fine. + */ + dword = pm_io_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_io_write32(PM_SPI_PAD_PU_PD, dword);
- dword = pm_io_read32(PM_ACPI_CONF); - dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; - pm_io_write32(PM_ACPI_CONF, dword); - } + dword = pm_io_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_io_write32(PM_ACPI_CONF, dword); } diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index f5890d4..976bc69 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -48,6 +48,7 @@ void test_svc_calls(void); uint32_t unmap_fch_devices(void); uint32_t verstage_soc_early_init(void); +void verstage_mainboard_espi_init(void); void verstage_soc_init(void); uintptr_t *map_spi_rom(void);
diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 3bfa3e9..f3b4256 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -24,6 +24,7 @@ extern char _bss_start, _bss_end;
void __weak verstage_mainboard_early_init(void) {} +void __weak verstage_mainboard_espi_init(void) {} void __weak verstage_mainboard_init(void) {} uint32_t __weak get_max_workbuf_size(uint32_t *size) { @@ -233,8 +234,11 @@ svc_debug_print("verstage_soc_early_init failed! -- rebooting\n"); vboot_reboot(); } - svc_debug_print("calling verstage_mainboard_early_init\n");
+ printk(BIOS_DEBUG, "calling verstage_mainboard_espi_init\n"); + verstage_mainboard_espi_init(); + + printk(BIOS_DEBUG, "calling verstage_mainboard_early_init\n"); verstage_mainboard_early_init();
svc_write_postcode(POSTCODE_LATE_INIT);
-
Paul Fagerburg (Code Review)