Change in ...coreboot[master]: cpu/intel: Use the common code to initialize the romstage timestamps
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30670
Change subject: cpu/intel: Use the common code to initialize the romstage timestamps ......................................................................
cpu/intel: Use the common code to initialize the romstage timestamps
In the bootblock timestamps are pushed to mm1 and mm2 registers which the romstage can now use to set up the initial timestamp.
Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/romstage.c M src/cpu/intel/haswell/romstage.c M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/roda/rk9/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch_common.c M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801gx/early_lpc.c M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/early_lpc.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c 37 files changed, 3 insertions(+), 214 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30670/1
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 5eba043..9d3144d 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -17,6 +17,7 @@ #include <cpu/x86/mtrr.h> #include <arch/symbols.h> #include <program_loading.h> +#include <timestamp.h>
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
@@ -59,6 +60,8 @@ */ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { + timestamp_init(base_timestamp); + timestamp_add_now(TS_START_ROMSTAGE); romstage_main(bist); } #endif diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index a25f883..c6020e1 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -77,9 +77,6 @@ int boot_mode; int wake_from_s3;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (params->bist == 0) enable_lapic();
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index a538e0f..de60fbb 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -237,9 +237,6 @@ int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 };
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index e0246a8..0151919 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -90,9 +90,6 @@ u8 boot_path = 0; u8 s3_resume;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 6f41b4c..31de960 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -188,9 +188,6 @@
u8 c_bsel = msr_get_fsb();
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index eb534ca..527f31b 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -73,9 +73,6 @@ u8 boot_path = 0; u8 s3_resume;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich10_enable_lpc(); mb_gpio_init(); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index bc04261..09629d5 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -148,9 +148,6 @@ u8 boot_path = 0; u8 s3_resume;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index 2d64bef..da23d55 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -88,9 +88,6 @@ int s3resume = 0; int boot_path;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 5ea41ea..cf5337f 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -88,9 +88,6 @@ u8 boot_path = 0; u8 s3_resume;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set up southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 18d856b..664a683 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -171,7 +171,6 @@ /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001;
- /* This should probably go into the ACPI enable trap */ /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ RCBA32(0x1e84) = 0x00020001; @@ -240,9 +239,6 @@ { int s3resume = 0;
- timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 6c1da82..34d056e 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -149,10 +149,6 @@ { int s3resume = 0, boot_mode = 0;
- - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 4613c14..0121f18 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -134,9 +134,6 @@ u8 boot_path = 0; u8 s3_resume;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_gpio_init(); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 24bd8a2..09a28a4 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -204,9 +204,6 @@ { int s3resume = 0;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 459fb19..f613d40 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -37,7 +37,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0)
- /* Early mainboard specific GPIO setup */ static void mb_gpio_init(void) { @@ -95,9 +94,6 @@ int s3resume = 0; int boot_path;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 6f0e419..2e629ca 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -129,10 +129,6 @@ { int s3resume = 0, boot_mode = 0;
- - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 6e9d034..a6a65b6 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -84,9 +84,6 @@ u8 boot_path = 0; u8 s3_resume;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 36aa149..aa8c50e 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -75,9 +75,6 @@ u8 boot_path = 0; u8 s3_resume;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich10_enable_lpc(); mb_gpio_init(); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 144872d..2b5af3d 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -294,10 +294,6 @@ { int s3resume = 0;
- - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 6d93112..1a392fa 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -68,9 +68,6 @@ int err; u16 reg16;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* basic northbridge setup, including MMCONF BAR */ gm45_early_init();
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 3b806f9..7807bb6 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -170,10 +170,6 @@ int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
- - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index 149a45d..f264e35 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -70,9 +70,6 @@ u8 boot_path = 0; u8 s3_resume;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 8176fad..0669568 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -34,7 +34,6 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0)
- static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -56,9 +55,6 @@ int cbmem_initted; u16 reg16;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* basic northbridge setup, including MMCONF BAR */ gm45_early_init();
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index d6674fe..a30601f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -168,10 +168,6 @@ int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
- - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 20dbaba..130dcda 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -170,10 +170,6 @@ int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
- - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 6e9cc83..ea8bf2d 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -213,10 +213,6 @@ { int s3resume = 0;
- - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 1bcfd62..3080130 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -107,7 +107,6 @@ /* Exit configuration state. */ pnp_exit_conf_state(sio);
- /* Enable decoding of 0x600-0x60f through lpc. */ pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601);
@@ -123,9 +122,6 @@ int cbmem_initted; u16 reg16;
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - /* basic northbridge setup, including MMCONF BAR */ gm45_early_init();
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 7345443..26f4977 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -53,9 +53,6 @@ halt (); }
- timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - if (bist == 0) enable_lapic();
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 8541903..673f0c7 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -14,20 +14,8 @@ */
#include <arch/io.h> -#include <cpu/x86/tsc.h> #include "pch.h"
-static void store_initial_timestamp(void) -{ - /* On Cougar Point we have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - /* * Enable Prefetching and Caching. */ @@ -80,8 +68,6 @@
static void bootblock_southbridge_init(void) { - store_initial_timestamp(); - enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index 3e151fc..a9ec9b1 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -15,8 +15,6 @@ */
#include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include "pch.h" @@ -25,15 +23,6 @@ #include <rules.h>
#if ENV_ROMSTAGE -uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - int southbridge_detect_s3_resume(void) { u32 pm1_cnt; diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index c9c19a3..6d65df3 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -14,20 +14,8 @@ */
#include <arch/io.h> -#include <cpu/x86/tsc.h> #include "i82801gx.h"
-static void store_initial_timestamp(void) -{ - /* On i945/ICH7 we have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - static void enable_spi_prefetch(void) { u8 reg8; @@ -43,8 +31,6 @@
static void bootblock_southbridge_init(void) { - store_initial_timestamp(); - enable_spi_prefetch();
/* Enable RCBA */ diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c index 11da3ec..a52fb85 100644 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ b/src/southbridge/intel/i82801gx/early_lpc.c @@ -15,21 +15,10 @@ */
#include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <console/console.h> #include <arch/acpi.h> #include "i82801gx.h"
-uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - int southbridge_detect_s3_resume(void) { u32 reg32; diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index bb025b0..6252712 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -14,19 +14,6 @@ */
#include <arch/io.h> -#include <cpu/x86/tsc.h> - -static void store_initial_timestamp(void) -{ - /* - * We have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -}
static void enable_spi_prefetch(void) { @@ -43,6 +30,5 @@
static void bootblock_southbridge_init(void) { - store_initial_timestamp(); enable_spi_prefetch(); } diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 7c4dafa..c40f9b7 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -15,19 +15,8 @@ */
#include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include "i82801ix.h"
-uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - void i82801ix_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 115555c..cc685c4 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,21 +14,8 @@ */
#include <arch/io.h> -#include <cpu/x86/tsc.h> #include "i82801jx.h"
-static void store_initial_timestamp(void) -{ - /* - * We have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - static void enable_spi_prefetch(void) { u8 reg8; @@ -44,7 +31,6 @@
static void bootblock_southbridge_init(void) { - store_initial_timestamp(); enable_spi_prefetch();
/* Enable RCBA */ diff --git a/src/southbridge/intel/i82801jx/early_lpc.c b/src/southbridge/intel/i82801jx/early_lpc.c index 74f0ee2..a59fdcc 100644 --- a/src/southbridge/intel/i82801jx/early_lpc.c +++ b/src/southbridge/intel/i82801jx/early_lpc.c @@ -15,21 +15,10 @@ */
#include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <console/console.h> #include <arch/acpi.h> #include "i82801jx.h"
-uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - int southbridge_detect_s3_resume(void) { u32 reg32; diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 20d0ee3..f87ebe3 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -14,20 +14,8 @@ */
#include <arch/io.h> -#include <cpu/x86/tsc.h> #include "pch.h"
-static void store_initial_timestamp(void) -{ - /* On Cougar Point we have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - /* * Enable Prefetching and Caching. */ @@ -83,8 +71,6 @@
static void bootblock_southbridge_init(void) { - store_initial_timestamp(); - map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc(); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 27a3b29..aae761c 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -18,8 +18,6 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci_def.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <elog.h> #include "pch.h" #include "chip.h" @@ -68,15 +66,6 @@ printk(BIOS_DEBUG, " done.\n"); }
-uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - static int sleep_type_s3(void) { u32 pm1_cnt;
-
Arthur Heymans (Code Review)