Attention is currently required from: Bora Guvendik, Pranava Y N.
Hello Bora Guvendik, build bot (Jenkins), Pranava Y N,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/86154?usp=email
to review the following change.
Change subject: Revert "mb/google/fatcat: Enable SAGv" ......................................................................
Revert "mb/google/fatcat: Enable SAGv"
This reverts commit 1e720b0a9b1cf35b9581824a47d57477a2b10a7f.
Reason for revert: Resulted into MRC hang with ES1 SoC. Need to revert SaGv CL to unblock fatcat boot with ES1 SoC.
Change-Id: I50041d6289b2d33aea5532ff563d32f09403d91b --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/86154/1
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index ec87353..b9dcbbd 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -30,9 +30,6 @@ register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
- # Enable SAGv - register "sagv" = "SAGV_ENABLED" - # Enable s0ix register "s0ix_enable" = "false"