Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79726?usp=email )
Change subject: mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800 ......................................................................
mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800
The setting was reduced to 666 for native raminit in commit 7039edd2da30 (SNB+MRC boards: Migrate MRC settings to devicetree) based on boot test results at the time.
With more changes merged, additional native raminit tests were done on p8z77-m. It is now possible for previously failing memory configurations to operate at full speed. This, combined with multiple reports on gerrit that this family does work at 800, warrants returning the setting to what it was.
Change-Id: I1fbe9c8d076fcd633f71424d60585681c40677c4 Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/79726 Reviewed-by: Matt DeVillier matt.devillier@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asus/p8x7x-series/devicetree.cb 1 file changed, 1 insertion(+), 2 deletions(-)
Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 192b4bd..4052cf4 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -4,8 +4,7 @@ # All MRC-capable boards in family (P8Z77-M[ PRO]) lists supported # DIMMs down to 1.25v register "ddr3lv_support" = "1" - # FIXME: Nothing can run native at 800MHz on p8z77-m, others may have same problem - register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" + register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
register "usb_port_config" = "{