Change in coreboot[master]: soc/intel/alderlake: add support for external source clock

[Cliff Huang (Code Review)]

Attention is currently required from: Bora Guvendik, Cliff Huang, Subrata Banik, Tim Wawrzynczak.
Hello Bora Guvendik, Anil Kumar K, build bot (Jenkins), Cliff Huang, Subrata Banik, Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63943

to look at the new patch set (#7).

Change subject: soc/intel/alderlake: add support for external source clock
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soc/intel/alderlake: add support for external source clock

Support up to 10 PCIe source clock out, including source clock out 7, 8, 9.
This allows boards to use source clock 7, 8, 9.

BUG=b:233252409
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang 
Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/63943/7