[XS] Change in coreboot[main]: soc/intel/braswell/Kconfig: Correct CONFIG_DCACHE_RAM_SIZE

[Frans Hendriks (Code Review)]

Attention is currently required from: Arthur Heymans, Erik van den Bogaert, Felix Held, Paul Menzel, Shelley Chen.

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82256?usp=email )

Change subject: soc/intel/braswell/Kconfig: Correct CONFIG_DCACHE_RAM_SIZE
......................................................................

Patch Set 3:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/82256/comment/de900910_16114c0d :
PS2, Line 9: used'is
> Please add a space.

Done

https://review.coreboot.org/c/coreboot/+/82256/comment/ec81f0da_5a69dd20 :
PS2, Line 13:
> This reverts commit 156bc6f47a7c (soc/intel/braswell: Increase dcache size). […]

Added revert in comment.
FSP always use fixed 0x4000 AFAIK. The commit you refer, contains info that Braswell can be build, nothing around testing on real HW.