Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48161 )
Change subject: lenovo/g505s: properly program the IRQ tables ......................................................................
lenovo/g505s: properly program the IRQ tables
IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for Lenovo G505S: all the fam15h boards have these "bad IRQs". OS like Linux still finds a way, but Kolibri can't see the IRQ table.
With this change applied: * G505S boots fine to Linux - no angry IRQ-related messages at dmesg; * KolibriOS sees 18 IRQs in a table and could successfully attach a driver to Atheros QCA8172 onboard Ethernet controller with an IRQ 3.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: Ifaa8b84b98453e5c372ea12833f16b43bf4a0dbd --- M src/mainboard/lenovo/g505s/mainboard.c M src/mainboard/lenovo/g505s/mptable.c 2 files changed, 185 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/48161/1
diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index d900c94..c7b95dc 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -7,8 +7,54 @@ #include <cpu/x86/smm.h> #include <device/device.h>
+#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <northbridge/amd/agesa/family15tn/pci_devs.h> #include <southbridge/amd/agesa/hudson/smi.h>
+extern const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE]; +extern const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE]; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ picr_data[PIRQ_A] if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D} }, */ + {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 4 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} } /* USB OHCI4: 0:14.05 - IRQ 5 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + static void pavilion_cold_boot_init(void) { /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ @@ -21,6 +67,9 @@ { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); + hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); global_smi_enable();
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index 5d8eb4d..d327580 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -5,23 +5,56 @@ #include <arch/smp/mpspec.h> #include <stdint.h> #include <string.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <drivers/generic/ioapic/chip.h>
-u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F +/* + * Based on 51205_Bolton_FCH_BIOS_Dev_Guide.pdf. Acronyms: + * + * SCI - System Controller Interrupt, + * SMBUS - System Management Bus, + * ASF - Advanced Synchronization Facility, + * HDA - HD Audio, + * SD - SD Flash Controller, + * GEC - Gigabit Ethernet Controller, + * PerMon - Performance Monitor, + * IMC - Integrated Memory Controller, + * GPP - PCIe General Purpose Ports. + */ + +const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0xAA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x05, 0x04, 0x05, + /* IDE, SATA */ + [0x40] = 0x1F, 0x07, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F }; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 + +const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x1F, 0x1F, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, + /* IDE, SATA */ + [0x40] = 0x1F, 0x13, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F };
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) @@ -46,7 +79,6 @@ { struct mp_config_table *mc; int bus_isa; - u8 byte;
/* * By the time this function gets called, the IOAPIC registers @@ -56,77 +88,121 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+ /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8);
+ /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc);
- //mptable_write_buses(mc, NULL, &bus_isa); + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + // mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA ");
- /* I/O APICs: APIC ID Version State Address */ + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
- /* IOMMU */ - PCI_INT(0x0, 0x00, 0x0, 0x10); - PCI_INT(0x0, 0x00, 0x1, 0x11); - PCI_INT(0x0, 0x00, 0x2, 0x12); - PCI_INT(0x0, 0x00, 0x3, 0x13); + /* IOMMU: 0:00.02 - IRQ 3 */ + PCI_INT(0x0, 0x00, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x00, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x00, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x00, 0x3, intr_data_ptr[PIRQ_D]);
- /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]); + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]);
- /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ + PCI_INT(0x0, 0x04, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x04, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x04, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x04, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 4 */ + PCI_INT(0x0, 0x05, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x05, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x05, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x05, 0x3, intr_data_ptr[PIRQ_A]);
- /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + /* USB XHCI: 0:10.00 - IRQ 5 */ + PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); + /* SATA: 0:11.00 - IRQ 7 */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + /* USB OHCI1: 0:12.00 - IRQ 5 */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + /* USB EHCI1: 0:12.02 - IRQ 4 */ + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + /* USB OHCI2: 0:13.00 - IRQ 5 */ + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + /* USB EHCI2: 0:13.02 - IRQ 4 */ + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + /* USB OHCI3: 0:16.00 - IRQ 5 */ + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + /* USB EHCI3: 0:16.02 - IRQ 4 */ + PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + /* USB OHCI4: 0:14.05 - IRQ 5 */ + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_C]);
- /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
- /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + /* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x2, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x2, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x2, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x3, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x3, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x3, 0x0, 0x3, intr_data_ptr[PIRQ_A]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */
/* Compute the checksums */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48161 )
Change subject: lenovo/g505s: properly program the IRQ tables ......................................................................
Patch Set 1:
(18 comments)
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... File src/mainboard/lenovo/g505s/mainboard.c:
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 31: {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 32: {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 33: {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 34: {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 35: {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 36: {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 37: {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 38: {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 39: {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 40: {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 41: {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 42: {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 43: {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 44: {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 45: {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 46: {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} } /* USB OHCI4: 0:14.05 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... File src/mainboard/lenovo/g505s/mptable.c:
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 132: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 202: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) line over 96 characters
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48161 )
Change subject: lenovo/g505s: properly program the IRQ tables ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... File src/mainboard/lenovo/g505s/mptable.c:
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 180: PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_C]); 1) You can just loop over the discovered PCI devices, find out which INT they are using and look that up in mainboard_intr_data[].
2) Ack, will try using this code from ./src/southbridge/intel/common/acpi_pirq_gen.c: ... pci_dev = PCI_SLOT(dev->path.pci.devfn); int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); ...
https://review.coreboot.org/c/coreboot/+/48161/1/src/mainboard/lenovo/g505s/... PS1, Line 183: 0x1 This is dynamically allocated so you want to look at ->link_list->secondary of the PCIe devices.
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48161 )
Change subject: lenovo/g505s: properly program the IRQ tables ......................................................................
Patch Set 1:
Helpful comments by Arthur Heymans that are still on TODO list:
"All this ACPI, hardware config, mptable and pirqtable synchronisation is just messy. With Intel we solved this by generating most at runtime: see southbridge/intel/common/acpi_pirq_data.c . That solution is quite general and could easily be ported to AMD."
Today I tried using the results obtained by this cycle (see below) - that's what the "dynamic generation" would've given me - and have updated all the IRQ tables & routing accordingly. However, despite my best efforts, a laptop is running super slow (plagued by bad IRQs?) and doesn't detect SATA at all.
ACPI_PIRQ_GEN: PCI: 00:00.0: int_pin=0 int_pin-pirq_a=0 ACPI_PIRQ_GEN: PCI: 00:00.2: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:01.0: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:01.1: int_pin=2 int_pin-pirq_a=2 ACPI_PIRQ_GEN: PCI: 00:02.0: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:04.0: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:05.0: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:11.0: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:12.0: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:12.2: int_pin=2 int_pin-pirq_a=2 ACPI_PIRQ_GEN: PCI: 00:13.0: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:13.2: int_pin=2 int_pin-pirq_a=2 ACPI_PIRQ_GEN: PCI: 00:14.0: int_pin=0 int_pin-pirq_a=0 ACPI_PIRQ_GEN: PCI: 00:14.2: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:14.3: int_pin=0 int_pin-pirq_a=0 ACPI_PIRQ_GEN: PCI: 00:14.4: int_pin=0 int_pin-pirq_a=0 ACPI_PIRQ_GEN: PCI: 00:14.5: int_pin=3 int_pin-pirq_a=3 ACPI_PIRQ_GEN: PCI: 00:16.0: int_pin=1 int_pin-pirq_a=1 ACPI_PIRQ_GEN: PCI: 00:16.2: int_pin=2 int_pin-pirq_a=2 ACPI_PIRQ_GEN: PCI: 00:18.0: int_pin=0 int_pin-pirq_a=0 ACPI_PIRQ_GEN: PCI: 00:18.1: int_pin=0 int_pin-pirq_a=0 ACPI_PIRQ_GEN: PCI: 00:18.2: int_pin=0 int_pin-pirq_a=0 ACPI_PIRQ_GEN: PCI: 00:18.3: int_pin=0 int_pin-pirq_a=0 ACPI_PIRQ_GEN: PCI: 00:18.4: int_pin=0 int_pin-pirq_a=0 ACPI_PIRQ_GEN: PCI: 00:18.5: int_pin=0 int_pin-pirq_a=0
"What you want to is get the INT pin from PCI config and look that up in the 0xC00 IO config space. (This is sort of the equivalent of what Intel has in RCBA, see southbridge/intel/common/rcba_pirq.c)"
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48161 )
Change subject: lenovo/g505s: properly program the IRQ tables ......................................................................
Patch Set 1:
Is it possible to merge this static routing, if it's always working and better than the old routing?
P.S. Meanwhile I could try to do a similar change for ASUS A88XM-E - another fam15h board with bad IRQs. ASUS AM1I-A fam16h is better but also not ideal
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48161 )
Change subject: lenovo/g505s: properly program the IRQ tables ......................................................................
Patch Set 2:
(18 comments)
File src/mainboard/lenovo/g505s/mainboard.c:
https://review.coreboot.org/c/coreboot/+/48161/comment/618bf956_843bfb52 PS2, Line 31: {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/fff8ef4b_df6687ca PS2, Line 32: {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/7e7e34fc_80873f71 PS2, Line 33: {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/5e6a92b6_9fa698cc PS2, Line 34: {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/24d60337_87b132ca PS2, Line 35: {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to Eth 2:00.00: 0:04.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/747f692e_308aa86e PS2, Line 36: {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to WiFi 3:00.00: 0:05.00 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/d7bd002f_030b61d1 PS2, Line 37: {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/5516986b_bbaba22f PS2, Line 38: {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/0f9825c2_652bc9dd PS2, Line 39: {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/8b140947_6a2e8fdd PS2, Line 40: {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/92680783_977ca681 PS2, Line 41: {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/388968a6_10df270b PS2, Line 42: {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/20d6ab86_2a2c73f5 PS2, Line 43: {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/a4d1e5ae_51a11ec9 PS2, Line 44: {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/26f11575_21e1186f PS2, Line 45: {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/11d43320_15a5b64c PS2, Line 46: {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} } /* USB OHCI4: 0:14.05 - IRQ 5 */ line over 96 characters
File src/mainboard/lenovo/g505s/mptable.c:
https://review.coreboot.org/c/coreboot/+/48161/comment/2f7f6a21_d4004e94 PS2, Line 132: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/48161/comment/894287be_63979246 PS2, Line 202: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) line over 96 characters
Mike Banon has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48161 )
Change subject: lenovo/g505s: properly program the IRQ tables ......................................................................
Abandoned
Abandoned in favor of CB:58750
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build bot (Jenkins) (Code Review) -
Mike Banon (Code Review)