Change in coreboot[master]: soc/intel/cnl: Add provision to configure SD controller write protect...

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

soc/intel/cnl: Add provision to configure SD controller write protect pin

FSP allows provison to configure SD controller WP pin, however some
of board design might choose not to use the SD WP pin from SD card
controller. This implementation adds a config that allows to enable
/disable SD controller WP pin configuration from FSP.

Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/34900/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 71aa208..4056817 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -186,6 +186,8 @@
    uint8_t EmmcHs400RxStrobeDll1;
    /* 0-78: number of active delay for TX data, unit is 125 psec */
    uint8_t EmmcHs400TxDataDll;
+	/* Enable/disable SD Card Write Protect Pin */
+	uint8_t ScsSdCardWpPinEnabled;

/* Integrated Sensor */
    uint8_t PchIshEnable;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0f27c47..612e582 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -336,6 +336,7 @@
    	params->ScsSdCardEnabled = dev->enabled;
    	params->SdCardPowerEnableActiveHigh =
    		CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
+		params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled;
    }

dev = pcidev_path_on_root(PCH_DEVFN_UFS);

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34900

to look at the new patch set (#2).

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

soc/intel/cnl: Add provision to configure SD controller write protect pin

Cometlake FSP allows provison to configure SD controller WP pin, As
some of board design might choose not to use the SD WP pin from SD
card controller. This implementation adds a config that allows to
enable/disable SD controller WP pin configuration from FSP.

Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/34900/2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34900/2/src/soc/intel/cannonlake/ch... 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/c/coreboot/+/34900/2/src/soc/intel/cannonlake/ch... 
PS2, Line 189: Enable/disable SD Card Write Protect Pin
Enable/disable SD Card Write Protect Pin Configuration? Also, mention that this is only for CML?

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, Paul Fagerburg, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34900

to look at the new patch set (#3).

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

soc/intel/cnl: Add provision to configure SD controller write protect pin

Cometlake FSP allows provison to configure SD controller WP pin, As
some of board design might choose not to use the SD WP pin from SD
card controller. This implementation adds a config that allows to
enable/disable SD controller WP pin configuration from FSP.

Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/34900/3

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34900/2/src/soc/intel/cannonlake/ch... 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/c/coreboot/+/34900/2/src/soc/intel/cannonlake/ch... 
PS2, Line 189: Enable/disable SD Card Write Protect Pin
> Enable/disable SD Card Write Protect Pin Configuration? Also, mention that this is only for CML?

Ok. Done.

[Paul Fagerburg (Code Review)]

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

Patch Set 3: Code-Review+1

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

Patch Set 3: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/34900/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34900/3//COMMIT_MSG@13 
PS3, Line 13: 
BUG=?

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, Paul Fagerburg, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34900

to look at the new patch set (#4).

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

soc/intel/cnl: Add provision to configure SD controller write protect pin

Cometlake FSP allows provison to configure SD controller WP pin, As
some of board design might choose not to use the SD WP pin from SD
card controller. This implementation adds a config that allows to
enable/disable SD controller WP pin configuration from FSP.

BUG=b:123907904

Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/34900/4

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

Patch Set 4:

(1 comment)
> Patch Set 3: Code-Review+2
>
> (1 comment)

https://review.coreboot.org/c/coreboot/+/34900/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34900/3//COMMIT_MSG@13 
PS3, Line 13:
> BUG=?

Ok. Updated.

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34900/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34900/3//COMMIT_MSG@13 
PS3, Line 13:
> Ok. Updated.

Done

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

Patch Set 4: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
......................................................................

soc/intel/cnl: Add provision to configure SD controller write protect pin

Cometlake FSP allows provison to configure SD controller WP pin, As
some of board design might choose not to use the SD WP pin from SD
card controller. This implementation adds a config that allows to
enable/disable SD controller WP pin configuration from FSP.

BUG=b:123907904

Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9
Signed-off-by: Aamir Bohra 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34900
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Paul Fagerburg 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved
  Paul Fagerburg: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 71aa208..fa98cd4 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -186,6 +186,8 @@
    uint8_t EmmcHs400RxStrobeDll1;
    /* 0-78: number of active delay for TX data, unit is 125 psec */
    uint8_t EmmcHs400TxDataDll;
+	/* Enable/disable SD card write protect pin configuration on CML */
+	uint8_t ScsSdCardWpPinEnabled;

/* Integrated Sensor */
    uint8_t PchIshEnable;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0f27c47..494c1db 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -336,6 +336,9 @@
    	params->ScsSdCardEnabled = dev->enabled;
    	params->SdCardPowerEnableActiveHigh =
    		CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
+#if CONFIG(SOC_INTEL_COMETLAKE)
+		params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled;
+#endif
    }

dev = pcidev_path_on_root(PCH_DEVFN_UFS);