Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59853 )
Change subject: soc/intel/tigerlake: Define soc_get_pcie_rp_type ......................................................................
soc/intel/tigerlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for tigerlake.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 --- M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/pcie_rp.c 3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59853/1
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index f74706e..52eaecf 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -117,4 +117,9 @@ PCIE_RP_PCH, };
+/* + * For PCIe RTD3 support, each SoC that uses it must implement this function. + */ +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev); + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 6da5e00..25a1d65 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += lpm.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += soundwire.c diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c new file mode 100644 index 0000000..f8d4109 --- /dev/null +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } +}; + +static const struct pcie_rp_group cpu_rp_groups[] = { + { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 }, + { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1 }, + { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 }, + { 0 } +}; + +static bool is_part_of_group(const struct device *dev, + const struct pcie_rp_group *groups) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn); + const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn); + const struct pcie_rp_group *group; + unsigned int i; + unsigned int fn; + + for (group = groups; group->count; ++group) { + for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { + if (slot_to_find == group->slot && fn_to_find == fn) + return true; + } + } + + return false; +} + +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) +{ + if (is_part_of_group(dev, pch_lp_rp_groups)) + return PCIE_RP_PCH; + + if (is_part_of_group(dev, cpu_rp_groups)) + return PCIE_RP_CPU; + + return PCIE_RP_UNKNOWN; +}