[M] Change in coreboot[master]: soc/intel/broadwell: Consolidate SPD handling - coreboot-gerrit

5 Sep 2022


      Attention is currently required from: Angel Pons.
Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55811 )
Change subject: soc/intel/broadwell: Consolidate SPD handling
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Patch Set 14:
(1 comment)
File src/mainboard/intel/wtm2/pei_data.c:
https://review.coreboot.org/c/coreboot/+/55811/comment/d2329654_67bf7f49 
PS14, Line 8: spdi->addresses[0] = 0x51;
            : 	spdi->addresses[2] = 0x51;
looks like there is a typo.
Is it possible the have same address for both dimms ?
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Gerrit-Project: coreboot
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