26 May
2019
26 May
'19
8:31 a.m.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22776 )
Change subject: intel/sandybridge: Make timC training more robust. ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/ra... PS3, Line 1580: /* With command training not happend yet, the lane can 'happend' may be misspelled - perhaps 'happened'?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71
Gerrit-Change-Number: 22776
Gerrit-PatchSet: 3
Gerrit-Owner: Tobias Diedrich ranma+coreboot@tdiedrich.de
Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: Evgeny Zinoviev me@ch1p.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Reviewer: Tobias Diedrich ranma+coreboot@tdiedrich.de
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Sun, 26 May 2019 06:31:54 +0000
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Gerrit-MessageType: comment
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