Change in ...coreboot[master]: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads

[Furquan Shaikh (Code Review)]

Hello Aaron Durbin, Duncan Laurie, Shelley Chen,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31251

to look at the new patch set (#2).

Change subject: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads
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mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads

This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.

BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.

Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/hatch/ramstage.c
M src/mainboard/google/sarien/ramstage.c
2 files changed, 4 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31251/2