Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47042 )

Change subject: sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function
......................................................................

sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function

Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/lynxpoint/lpc.c
1 file changed, 19 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/47042/1

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 2e4dcd0..373bafc 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -73,6 +73,25 @@
 #endif
 }

+static void enable_hpet(struct device *const dev)
+{
+	u32 reg32;
+	size_t i;
+
+	/* Assign unique bus/dev/fn for each HPET */
+	for (i = 0; i < 8; ++i)
+		pci_write_config16(dev, LPC_HnBDF(i),
+			PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
+
+	/* Move HPET to default address 0xfed00000 and enable it */
+	reg32 = RCBA32(HPTC);
+	reg32 |= (1 << 7); // HPET Address Enable
+	reg32 &= ~(3 << 0);
+	RCBA32(HPTC) = reg32;
+	/* Read it back to stick. It's affected by posted write syndrome. */
+	RCBA32(HPTC);
+}
+
 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  * 0x00 - 0000 = Reserved
  * 0x01 - 0001 = Reserved
@@ -359,25 +378,6 @@
    RCBA32_OR(0x33c8, (1 << 15));
 }

-static void enable_hpet(struct device *const dev)
-{
-	u32 reg32;
-	size_t i;
-
-	/* Assign unique bus/dev/fn for each HPET */
-	for (i = 0; i < 8; ++i)
-		pci_write_config16(dev, LPC_HnBDF(i),
-			PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
-
-	/* Move HPET to default address 0xfed00000 and enable it */
-	reg32 = RCBA32(HPTC);
-	reg32 |= (1 << 7); // HPET Address Enable
-	reg32 &= ~(3 << 0);
-	RCBA32(HPTC) = reg32;
-	/* Read it back to stick. It's affected by posted write syndrome. */
-	RCBA32(HPTC);
-}
-
 static void enable_clock_gating(struct device *dev)
 {
    /* LynxPoint Mobile */

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47042 )

Change subject: sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function
......................................................................

Patch Set 4: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47042 )

Change subject: sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function
......................................................................

sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function

Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47042
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/lynxpoint/lpc.c
1 file changed, 19 insertions(+), 19 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 4464f91..232ad2e 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -70,6 +70,25 @@
 #endif
 }

+static void enable_hpet(struct device *const dev)
+{
+	u32 reg32;
+	size_t i;
+
+	/* Assign unique bus/dev/fn for each HPET */
+	for (i = 0; i < 8; ++i)
+		pci_write_config16(dev, LPC_HnBDF(i),
+			PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
+
+	/* Move HPET to default address 0xfed00000 and enable it */
+	reg32 = RCBA32(HPTC);
+	reg32 |= (1 << 7); // HPET Address Enable
+	reg32 &= ~(3 << 0);
+	RCBA32(HPTC) = reg32;
+	/* Read it back to stick. It's affected by posted write syndrome. */
+	RCBA32(HPTC);
+}
+
 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  * 0x00 - 0000 = Reserved
  * 0x01 - 0001 = Reserved
@@ -371,25 +390,6 @@
    RCBA32_OR(0x33c8, (1 << 15));
 }

-static void enable_hpet(struct device *const dev)
-{
-	u32 reg32;
-	size_t i;
-
-	/* Assign unique bus/dev/fn for each HPET */
-	for (i = 0; i < 8; ++i)
-		pci_write_config16(dev, LPC_HnBDF(i),
-			PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
-
-	/* Move HPET to default address 0xfed00000 and enable it */
-	reg32 = RCBA32(HPTC);
-	reg32 |= (1 << 7); // HPET Address Enable
-	reg32 &= ~(3 << 0);
-	RCBA32(HPTC) = reg32;
-	/* Read it back to stick. It's affected by posted write syndrome. */
-	RCBA32(HPTC);
-}
-
 static void enable_clock_gating(struct device *dev)
 {
    /* LynxPoint Mobile */