Change in coreboot[master]: soc/intel/jasperlake: correct IRQ routing Jasper Lake

[Ronak Kanabar (Code Review)]

Hello V Sowmya, Varshit B Pandya, Patrick Georgi, Maulik V Vaghela, Subrata Banik, Aamir Bohra, Rizwan Qureshi, Patrick Rudolph, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41404

to look at the new patch set (#5).

Change subject: soc/intel/jasperlake: correct IRQ routing Jasper Lake
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soc/intel/jasperlake: correct IRQ routing Jasper Lake

Current Interrupt setting use 2nd parameters as device function number.
- Correct as interrupt pin number according to _PRT package format.
  {Address, pin, Source, Source index}

BUG=None
BRANCH=None
TEST=Build and boot JSLRVP Verify Interrupt mappings are same as PCI
INTR(0x3C) register and no interrupt storm is seen

Change-Id: I21462c6befea310a49eecf9ad1b5c8770eccd5bd
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/jasperlake/acpi/pci_irqs.asl
M src/soc/intel/jasperlake/include/soc/irq.h
2 files changed, 56 insertions(+), 108 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/41404/5