[M] Change in coreboot[master]: soc/intel/broadwell: Consolidate SPD handling

[Nico Huber (Code Review)]

Attention is currently required from: Angel Pons.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55811 )

Change subject: soc/intel/broadwell: Consolidate SPD handling
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Patch Set 14:

(1 comment)

File src/mainboard/intel/wtm2/pei_data.c:

https://review.coreboot.org/c/coreboot/+/55811/comment/417b7bf2_2eeb9717 
PS14, Line 8: spdi->addresses[0] = 0x51;
            : 	spdi->addresses[2] = 0x51;
> looks like there is a typo.

I couldn't find information about WTM2. It could be an error and maybe
wasn't noticed because it works when both slots have compatible DIMMs
plugged in.
> Is it possible the have same address for both dimms ?

Not for DIMMs. But it's possible to have the same chips attached to both
channels (e.g. when DRAM is soldered down) and a single EEPROM for the
common configuration (and yes, sometimes soldered down DRAM comes with an
EEPROM *shrug*).